llvm-svn: 83174

for derived AsmPrinters to add another one.  In some cases, fixing this
removes the need to override the doInitialization method.

llvm-svn: 83170

llvm-svn: 83148

llvm-svn: 83145

the size of the saved frame pointer needs to be taken into account.

llvm-svn: 83136

Patch by Sylvere Teissier.

llvm-svn: 83135

section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.

llvm-svn: 83127

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

llvm-svn: 83122

llvm-svn: 83117

llvm-svn: 83083

llvm-svn: 83058

slot for the register scavenger when compiling Thumb1 functions.

llvm-svn: 83023

llvm-svn: 83008

unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006

Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

Disable rematting of it for now.

llvm-svn: 82975

This should be better than single load from constpool.

llvm-svn: 82948

operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.

llvm-svn: 82942

llvm-svn: 82909

llvm-svn: 82893

llvm-svn: 82838

llvm-svn: 82837

llvm-svn: 82836

llvm-svn: 82814

llvm-svn: 82805

 - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794

naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790

llvm-svn: 82788

llvm-svn: 82773

For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.

llvm-svn: 82767

instructions. This fixes a PowerPC bug exposed by some unrelated
changes I'm working on.

llvm-svn: 82743

interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.

Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.

For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.

llvm-svn: 82734

llvm-svn: 82716

llvm-svn: 82709

llvm-svn: 82657

llvm-svn: 82656

is also the name of their type, as declarations like "EVT EVT" look
really odd.

llvm-svn: 82654

default implementation.  Update comment on the default version, which made it
sound like most targets override it.  Currently only X86 and SystemZ override
this method.

llvm-svn: 82651

This fixes PR5031. Unfortunately, there is no small testcase :(

llvm-svn: 82643