When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.

llvm-svn: 78244

llvm-svn: 78086

llvm-svn: 77521

llvm-svn: 76727

llvm-svn: 76390

llvm-svn: 75566

llvm-svn: 75562

quad registers and the Q4PR class holds sets of 4 quad registers.

llvm-svn: 75309

This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919

caller-saved register.

llvm-svn: 73901

llvm-svn: 73734

ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095

Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.

llvm-svn: 72955

When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545

llvm-svn: 46930

llvm-svn: 45418

This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997

llvm-svn: 37897

llvm-svn: 36280

llvm-svn: 35021

llvm-svn: 34999

llvm-svn: 34711

llvm-svn: 34709

llvm-svn: 34701

llvm-svn: 33633

llvm-svn: 33455

llvm-svn: 33389

llvm-svn: 33353

llvm-svn: 31197

initial support for returning 64bit floating point numbers

llvm-svn: 30692

implement SINT_TO_FP

llvm-svn: 30673

llvm-svn: 29756

fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854

llvm-svn: 28301