llvm-svn: 145608

llvm-svn: 145607

llvm-svn: 145596

sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

llvm-svn: 145579

llvm-svn: 145578

llvm-svn: 145573

(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"

Fixes <rdar://problem/10482509>

llvm-svn: 145563

InstructionSimplify.cpp.  Other fixups as needed.
Part of rdar://10500969

llvm-svn: 145559

llvm-svn: 145556

llvm-svn: 145553

llvm-svn: 145530

remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525

Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.

<rdar://problem/10497732>.

llvm-svn: 145523

llvm-svn: 145517

llvm-svn: 145510

llvm-svn: 145508

llvm-svn: 145504

While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

llvm-svn: 145494

llvm-svn: 145493

X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).

llvm-svn: 145488

llvm-svn: 145487

llvm-svn: 145485

Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.

llvm-svn: 145483

Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.

llvm-svn: 145482

llvm-svn: 145470

change intended.

llvm-svn: 145468

llvm-svn: 145464

(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

llvm-svn: 145460

llvm-svn: 145458

llvm-svn: 145456

llvm-svn: 145454

tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451

llvm-svn: 145450

Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.

llvm-svn: 145448

llvm-svn: 145442

Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440

Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should not be changed inside the uses enumeration loop.

llvm-svn: 145432

attempt.  

llvm-svn: 145425

llvm-svn: 145422

llvm-svn: 145420