llvm-svn: 162524

llvm-svn: 162520

llvm-svn: 162518

They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

llvm-svn: 162517

Emit TableGen errors if guessInstructionProperties is 0 and
instruction properties can't be inferred from patterns.

Allow explicit instruction properties even when they can be inferred.

This patch doesn't change the TableGen output. Redundant properties
are not yet verified because the tree has errors.

llvm-svn: 162516

llvm-svn: 162515

llvm-svn: 162514

Fix undefined behavior (signed integer overflow) when Clang parses a hexfloat with an enormous exponent. Caught by an existing unit test + -ftrapv.

llvm-svn: 162505

llvm-svn: 162499

llvm-svn: 162498

output (we're emitting a specification already and the information
isn't changing) and we're not in old gdb compat mode.

Saves 1% on the debug information for a build of llvm.

Fixes rdar://11043421

llvm-svn: 162493

turned on and off separate from the platform if you're on darwin.

llvm-svn: 162487

we're using the darwin old gdb compat mode for emitting dwarf.

llvm-svn: 162486

No test case, this is a generalization of r160260.

llvm-svn: 162485

Keep track of the set/unset state of these bits along with their
true/false values, but treat '?' as '0' for now.

llvm-svn: 162461

Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

llvm-svn: 162460

These intrinsics don't have unmodeled side effects, they are just
stores.

llvm-svn: 162459

This should fix a -Wdocumentation warning.

llvm-svn: 162458

llvm-svn: 162454

llvm-svn: 162446

llvm-svn: 162438

with older gdbs on darwin.

rdar://10975874

llvm-svn: 162436

llvm-svn: 162435

rdar://10393214

llvm-svn: 162434

llvm-svn: 162433

llvm-svn: 162432

change in r162404.

llvm-svn: 162431

llvm-svn: 162428

llvm-svn: 162426

llvm-svn: 162422

llvm-svn: 162421

The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.

llvm-svn: 162420

the temporary register that was used to load the immediate. Currently, it always
returns register $at, but this will change if, in the future, we decide to use 
another register.

No changes in functionality.

llvm-svn: 162417

Mips16RegisterInfo/MipsSERegisterInfo. 

No changes in functionality.

llvm-svn: 162413

llvm-svn: 162411

When reporting an error for a defm, we would previously only report the
location of the outer defm, which is not always where the error is.

Now we also print the location of the expanded multiclass defs:

lib/Target/X86/X86InstrSSE.td:2902:12: error: foo
  defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
             ^
lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass
  defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
            ^
lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass
    def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
        ^

llvm-svn: 162409

The MCInst is immediately passed to the copy-constructor for local
storage, so there's no need for the parameter itself to be by-value.

llvm-svn: 162404

llvm-svn: 162402

llvm-svn: 162383

Assertion failed: (Start.isValid() == End.isValid() && "Start and end should 
either both be valid or both be invalid!")

when parsing inline asm.  SMLoc assumes that the first char * in the source is
invalid.  However, when parsing an inline asm the mnemonic is at this location.
I don't want to change SMLoc, so use a trivial workaround.

llvm-svn: 162381