Found by inspection.

llvm-svn: 127247

llvm-svn: 127246

testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.

Performance results:

roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated

john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES

Small compile time impact.

llvm-svn: 127208

llvm-svn: 127198

llvm-svn: 127197

expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193

llvm-svn: 127175

ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case

llvm-svn: 127106

In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.

llvm-svn: 127105

Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.

llvm-svn: 127104

llvm-svn: 127103

llvm-svn: 127102

This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101

llvm-svn: 127099

llvm-svn: 127090

llvm-svn: 127084

regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.

Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.

Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.

llvm-svn: 127067

llvm-svn: 127065

llvm-svn: 127038

llvm-svn: 127034

Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka

llvm-svn: 127032

llvm-svn: 127029

llvm-svn: 127027

llvm-svn: 127020

Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.

llvm-svn: 127019

llvm-svn: 127017

llvm-svn: 127005

llvm-svn: 127003

There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.

llvm-svn: 126998

A 'load <4 x i32>* null' crashes llc before this fix.

llvm-svn: 126995

llvm-svn: 126970

Patch by Zonr Chang!

llvm-svn: 126967

and siprintf is available on the target.

llvm-svn: 126940

llvm-svn: 126938

and siprintf is available on the target.

llvm-svn: 126937

llvm-svn: 126936

and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.

llvm-svn: 126935

llvm-svn: 126934

llvm-svn: 126930

Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915