Put this change back in after testing from Reid proved its innocence.  getSpillSize now returns value in bits

llvm-svn: 16102

llvm-svn: 16077

LiveVariables.

llvm-svn: 16076

runs after the initial run of the live interval analysis.

llvm-svn: 16075

investicated further as the linearscan variants don't really need
LiveVariables...

llvm-svn: 16074

Back out change to divide getSpillSize by 8 until I figure out why it breaks x86, which has register sizes in bits.

llvm-svn: 16073

llvm-svn: 16071

llvm-svn: 16070

register set anymore. Its users now use the MRegisterInfo API.

llvm-svn: 16061

llvm-svn: 16060

 Regression.CodeGen.Generic.2004-04-09-SameValueCoalescing.llx and the
code size problem.

This bug prevented us from doing most register coallesces.

llvm-svn: 16031

with emitting .xwords when not on an 8-byte boundary (.xword 0 is not the
same as 8 .byte 0's).  Because we do not know when or when we are not aligned,
just emit bytes like the old V9 asmprinter did.

llvm-svn: 16006

bytes.

llvm-svn: 15970

of getRegClass

llvm-svn: 15967

llvm-svn: 15906

Also, squash a use of TargetInstrInfo::isNop().

llvm-svn: 15905

llvm-svn: 15897

llvm-svn: 15894

llvm-svn: 15888

llvm-svn: 15880

llvm-svn: 15870

llvm-svn: 15868

hear it for ".".

llvm-svn: 15863

llvm-svn: 15845

llvm-svn: 15838

llvm-svn: 15834

llvm-svn: 15833

llvm-svn: 15830

llvm-svn: 15829

llvm-svn: 15828

llvm-svn: 15823

llvm-svn: 15784

llvm-svn: 15779

llvm-svn: 15777

llvm-svn: 15775

llvm-svn: 15774

allowed).

llvm-svn: 15766

llvm-svn: 15736

Add support for targets that must spill certain physregs at certain locations.

Patch contributed by Nate Begeman, slightly hacked by me.

llvm-svn: 15701

llvm-svn: 15693