llvm-svn: 146081

llvm-svn: 146059

llvm-svn: 145912

them.

llvm-svn: 145852

- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  

llvm-svn: 145113

nodes.

llvm-svn: 144841

llvm-svn: 144840

"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414

llvm-svn: 144372

llvm-svn: 144370

llvm-svn: 144368

llvm-svn: 143994

instruction definitions.

llvm-svn: 143989

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226

llvm-svn: 142220

llvm-svn: 142216

llvm-svn: 142214

llvm-svn: 142211

source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210

and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207

llvm-svn: 142205

llvm-svn: 141761

Remove unused classes.

llvm-svn: 141757

llvm-svn: 141743

instructions with two register operands derive from it.

llvm-svn: 141742

llvm-svn: 141737

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736

llvm-svn: 141720

llvm-svn: 141715

llvm-svn: 141708

llvm-svn: 141696

llvm-svn: 141695

llvm-svn: 141694

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608

for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603

instruction selector to generate them.

llvm-svn: 141471

llvm-svn: 141024

registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015