llvm-svn: 7823

llvm-svn: 7533

llvm-svn: 7497

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 5272

llvm-svn: 5220

llvm-svn: 5200

* Use new FunctionFrameInfo object to manage stack slots instead of doing
  it directly
* Adjust to new MRegisterInfo API
* Don't take a TM as a ctor argument
* Don't keep track of which callee saved registers are modified
* Don't emit prolog/epilog code or spill/restore code for callee saved regs
* Use new allocation_order_begin/end iterators to simplify dramatically the
  logic for picking registers to allocate
* Machine PHI nodes can no longer contain constant arguments

* Use a bitvector to keep track of registers used instead of a set
* Fix problem where explicitly referenced registers would be added to
  regsused set and never removed

llvm-svn: 5196

llvm-svn: 5144

llvm-svn: 5113

llvm-svn: 5103

llvm-svn: 5099

llvm-svn: 5081

Remvoe some dead code

llvm-svn: 5070

llvm-svn: 5067

register allocation

llvm-svn: 5066

the dependence on PhysRegClassMap

llvm-svn: 5064

llvm-svn: 5061

llvm-svn: 5060

llvm-svn: 5058

llvm-svn: 5057

llvm-svn: 5055

spills and reloads emitted

llvm-svn: 5054

llvm-svn: 5052

  function from normal regalloc code
* Make the regalloc for a block a function instead of part of runOnMachineBB, which
  makes it easier to see what's going on in runOnMBB.

llvm-svn: 5051

* Make allocateStackSpaceFor only allocate the right amount of space

llvm-svn: 5048

target register description classes.

llvm-svn: 5045

llvm-svn: 5044

llvm-svn: 5043

llvm-svn: 5035

llvm-svn: 5019

basic block, as there could be multiple.

llvm-svn: 5016

an instruction to avoid using them to allocate to other virtual registers.

llvm-svn: 5013

disappeared during the last checkin.

llvm-svn: 5007

llvm-svn: 5002

Also make all loads & stores 4-byte aligned for performance. ;)

llvm-svn: 4982

register-allocated them appropriately.

llvm-svn: 4976

llvm-svn: 4930

after the *current* instruction while keeping the iterator in the same
'logical' place.

llvm-svn: 4923

correctly: skipping instructions by incorrectly incrementing the pointer.

Also adds support for building a reg-to-regclass map, and splits the function
for saving register to stack into two, one suitable for virtual registers
(which also assigns it a physical register) and one for simply storing back
physical registers.

llvm-svn: 4898