llvm-svn: 97627

llvm-svn: 97626

llvm-svn: 97623

llvm-svn: 97617

long test(long x) { return (x & 123124) | 3; }

Currently compiles to:

_test:
        orl     $3, %edi
        movq    %rdi, %rax
        andq    $123127, %rax
        ret

This is because instruction and DAG combiners canonicalize

  (or (and x, C), D) -> (and (or, D), (C | D))

However, this is only profitable if (C & D) != 0. It gets in the way of the
3-addressification because the input bits are known to be zero.

llvm-svn: 97616

disassembly only.

llvm-svn: 97614

llvm-svn: 97612

llvm-svn: 97611

llvm-svn: 97610

llvm-svn: 97609

llvm-svn: 97608

llvm-svn: 97606

We still preprocess calls and fp return stuff.

llvm-svn: 97598

now that isel handles chains more aggressively.  This also
allows us to make isLegalToFold non-virtual.

llvm-svn: 97597

CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)

llvm-svn: 97596

llvm-svn: 97595

llvm-svn: 97594

Place the LSDA into the TEXT section on Mach-O. This saves space.

llvm-svn: 97592

xor pattern.  I have no plans to fix this XFAIL.

llvm-svn: 97587

llvm-svn: 97586

llvm-svn: 97585

llvm-svn: 97584

the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.

llvm-svn: 97582

llvm-svn: 97581

by loop depth and emit loop-invariant subexpressions outside of loops.
This speeds up MultiSource/Applications/viterbi and others.

llvm-svn: 97580

llvm-svn: 97578

llvm-svn: 97577

llvm-svn: 97576

to itself, even though this isn't wildly useful.

llvm-svn: 97574

SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573

Thanks Duncan!

llvm-svn: 97572

Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution
llvm-svn: 97571

llvm-svn: 97567

llvm-svn: 97565

llvm-svn: 97564

and nothing for AddressSpace, pass 0 for InsertBefore, "false" for ThreadLocal
and AddressSpace for AddressSpace.  Spotted by gcc-4.5.

llvm-svn: 97563

was that we weren't properly handling the case when interior
nodes of a matched pattern become dead after updating chain
and flag uses.  Now we handle this explicitly in 
UpdateChainsAndFlags.

llvm-svn: 97561

*does* delete ex-operands that become dead.

llvm-svn: 97559

llvm-svn: 97558

llvm-svn: 97557