llvm-svn: 27151

llvm-svn: 27149

non-predicate altivec compare intrinsics.

llvm-svn: 27143

intrinsics.

llvm-svn: 27142

llvm-svn: 27139

llvm-svn: 27136

CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC

llvm-svn: 27135

llvm-svn: 27127

llvm-svn: 27118

Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

llvm-svn: 27117

llvm-svn: 27116

llvm-svn: 27115

llvm-svn: 27112

llvm-svn: 27109

 <int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

llvm-svn: 27106

llvm-svn: 27081

llvm-svn: 27077

llvm-svn: 27069

modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

llvm-svn: 27068

comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.

llvm-svn: 27060

Regression/CodeGen/PowerPC/vec_zero.ll

llvm-svn: 27059

llvm-svn: 27049

llvm-svn: 27000

llvm-svn: 26995

llvm-svn: 26994

llvm-svn: 26991

Make the CBE and V9 backends create their own, since they're the only ones that use it.

llvm-svn: 26974

llvm-svn: 26944

_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943

which is shifted left two bits before use.  Instructions like STD use this
addressing mode.

llvm-svn: 26942

llvm-svn: 26935

llvm-svn: 26930

llvm-svn: 26926

llvm-svn: 26924

       lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.

llvm-svn: 26922

llvm-svn: 26917

llvm-svn: 26913

llvm-svn: 26912

disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr

llvm-svn: 26908

llvm-svn: 26907