functions. Set AddedComplexity to determine the order in which patterns are
matched.

This simplifies selection of floating point loads/stores.

No functionality change intended.

llvm-svn: 175300

of the old jit and which we don't intend to support in mips16 or micromips.
This dependency is for the testing of whether an instruction is a pseudo.

llvm-svn: 175297

support constant extension.

This patch doesn't introduce any functionality changes.

llvm-svn: 175280

This is essentially a stripped-down version of the ConstandIslands pass (which
always had these two functions), providing just the features necessary for
correctness.

In particular there needs to be a way to resolve the situation where a
conditional branch's destination block ends up out of range.

This issue crops up when self-hosting for AArch64.

llvm-svn: 175269

than we need to and some ELF linkers complain about directly accessing symbols
with default visibility.

llvm-svn: 175268

blocks. We still don't have consensus if we should try to change clang or
the standard, but llvm should work with compilers that implement the current
standard and mangle those functions.

llvm-svn: 175267

llvm-svn: 175264

This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

llvm-svn: 175258

In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

llvm-svn: 175257

not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 

llvm-svn: 175237

Unfortunately, I wasn't able to create a test case that demonstrates the
problem I was trying to fix with this patch.

llvm-svn: 175226

defined and used registers. Also add a few helper functions to simplify the
code. 

llvm-svn: 175224

llvm-svn: 175222

assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.

This patch uses TwoOperandAliasConstraint to add the two argument form.

It also fixes an 80-column formatting problem in:
  test/MC/ARM/neon-bitwise-encoding

<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions

llvm-svn: 175221

llvm-svn: 175220

1. Define and use function terminateSearch.
2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator.
3. Delete the line which checks whether an instruction is a pseudo. 

llvm-svn: 175219

llvm-svn: 175212

This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.

llvm-svn: 175205

-feature flag, instructions definitions, test cases

llvm-svn: 175196

The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.

In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and
add a special operand class for the parameter slots for type checking and
pretty printing.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175193

llvm-svn: 175189

This patch doesn't introduce any functionality changes.

llvm-svn: 175187

inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186

It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183

This allows MachineInstScheduler to reorder them, and thus make scheduling more
efficient.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175182

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175181

This fixes a couple of regressions on (probably not just) cayman

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175180

llvm-svn: 175176

If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.

This fixes test failures when AArch64 is the default target.

llvm-svn: 175172

Only comments affected. No code change at all.

llvm-svn: 175169

The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164

Added a test.

llvm-svn: 175144

Fixes assertion failure in newly added lit test. Might just be a bandaid that
needs to be revisited.

llvm-svn: 175139

llvm-svn: 175133

up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
 

llvm-svn: 175126

llvm-svn: 175121

Since functions with internal linkage don't have language linkage, it is valid
to overload them:

extern "C" {
       static int foo();
       static int foo(int);
}

So we mangle them.

llvm-svn: 175120

llvm-svn: 175107

llvm-svn: 175102

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096