llvm-svn: 50696

llvm-svn: 50695

ComputeMaskedBits handles, just use a 'default:'. This avoids
TargetLowering's list getting out of date with SelectionDAG's.

llvm-svn: 50693

ComputeMaskedBits.

llvm-svn: 50692

llvm-svn: 50687

llvm-svn: 50681

llvm-svn: 50677

llvm-svn: 50675

themselves weren't in the anonymous namespace.

llvm-svn: 50673

DemoteRegToStack doesn't work with MRVs yet, because it relies on the
ability to load/store things.

This fixes PR2285.

llvm-svn: 50667

llvm-svn: 50663

llvm-svn: 50660

llvm-svn: 50659

llvm-svn: 50654

ELF headers. The ELF writer still isn't generally usable though.

llvm-svn: 50652

llvm-svn: 50649

the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634

but should work. Work is in progress, more models will follow

llvm-svn: 50630

llvm-svn: 50621

llvm-svn: 50620

Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.

llvm-svn: 50619

using dyn_cast<> on already freed memory.

llvm-svn: 50618

llvm-svn: 50607

llvm-svn: 50604

Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.

llvm-svn: 50601

llvm-svn: 50600

llvm-svn: 50596

llvm-svn: 50591

llvm-svn: 50590

llvm-svn: 50586

llvm-svn: 50582

llvm-svn: 50578

llvm-svn: 50575

Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.

llvm-svn: 50574

llvm-svn: 50564

llvm-svn: 50562

llvm-svn: 50561

llvm-svn: 50558

from x86-64 calling convention work.

llvm-svn: 50545

fixes the 254.gap regression on x86 and the 403.gcc regression on x86-64.

llvm-svn: 50537