via vectors.

Part of rdar://9643582

llvm-svn: 134079

Drop the FpMov instructions, use plain COPY instead.

Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.

This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.

As a bonus we handle floating point inline assembly correctly now.

llvm-svn: 134018

llvm-svn: 133874

<rdar://problem/9483883>

llvm-svn: 133858

overheads.  No functional change intended.

llvm-svn: 133824

llvm-svn: 133726

llvm-svn: 133347

optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.

llvm-svn: 133080

No functional change.

Part of PR6965

llvm-svn: 132763

load.  rdar://problem/6373334

llvm-svn: 132696

rdar://problem/5993888

llvm-svn: 132606

Part of rdar://9119939

llvm-svn: 132510

llvm-svn: 132479

rdar://problem/6373334

llvm-svn: 132458

llvm-svn: 132424

llvm-svn: 132419

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388

llvm-svn: 132108

rdar://problem/6920088

llvm-svn: 132105

  non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
  when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.

rdar://9490949

llvm-svn: 131948

llvm-svn: 131709

llvm-svn: 131708

Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682

llvm-svn: 131664

Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.

llvm-svn: 131560

llvm-svn: 131471

llvm-svn: 131469

passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088

llvm-svn: 131467

Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
with two different types, in cases where the index and the ptr had different
types.

llvm-svn: 131461

llvm-svn: 131424

Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.

llvm-svn: 131179

llvm-svn: 131012

triple component.

llvm-svn: 129838

llvm-svn: 129813

Luis Felipe Strano Moraes!

llvm-svn: 129558

llvm-svn: 128586

llvm-svn: 128338

FIXME: Some cleanups would be needed.
llvm-svn: 128206

I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.

llvm-svn: 128181