llvm-svn: 129447

llvm-svn: 129446

llvm-svn: 129445

component names such as "engine" do not expand to "jit" and hence to
the native target libraries for external users.

Thanks to arrowdodger for reporting and diagnosing the problem.

llvm-svn: 129444

related tweaks to ExprMapKeyType.

llvm-svn: 129443

llvm-svn: 129442

llvm-svn: 129441

llvm-svn: 129440

llvm-svn: 129439

llvm-svn: 129437

llvm-svn: 129436

llvm-svn: 129435

the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.

llvm-svn: 129432

llvm-svn: 129429

alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.

llvm-svn: 129428

llvm-svn: 129423

Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.

Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.

llvm-svn: 129421

llvm-svn: 129419

llvm-svn: 129417

Implement the ones that were missing in the asm streamer.

llvm-svn: 129413

rdar://problem/9273947

llvm-svn: 129411

The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409

registers for fast allocation.

Fixes rdar://9207598

llvm-svn: 129408

llvm-svn: 129407

llvm-svn: 129406

llvm-svn: 129405

values are also transmitted through branches which cause side effects to
be skipped altogether.

llvm-svn: 129404

llvm-svn: 129403

This mechanical patch moves type handling into CompileUnit from DwarfDebug. In case of multiple compile unit in one object file, each compile unit is responsible for its own set of type entries anyway. This refactoring makes this obvious.

llvm-svn: 129402

Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.

llvm-svn: 129401

llvm-svn: 129400

generators. It may improve robustness when testing from VS too.

Based on a patch by David Neto!

llvm-svn: 129398

In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391

Use a Bitvector instead, we didn't need the smaller memory footprint anyway.
This makes the greedy register allocator 10% faster.

llvm-svn: 129390

Add handling for tracking the relocations on symbols and resolving them.
Keep track of the relocations even after they are resolved so that if
the RuntimeDyld client moves the object, it can update the address and any
relocations to that object will be updated.

For our trival object file load/run test harness (llvm-rtdyld), this enables
relocations between functions located in the same object module. It should
be trivially extendable to load multiple objects with mutual references.

As a simple example, the following now works (running on x86_64 Darwin 10.6):


$ cat t.c
int bar() {
  return 65;
}

int main() {
  return bar();
}
$ clang t.c -fno-asynchronous-unwind-tables -o t.o -c
$ otool -vt t.o
t.o:
(__TEXT,__text) section
_bar:
0000000000000000  pushq %rbp
0000000000000001  movq  %rsp,%rbp
0000000000000004  movl  $0x00000041,%eax
0000000000000009  popq  %rbp
000000000000000a  ret
000000000000000b  nopl  0x00(%rax,%rax)
_main:
0000000000000010  pushq %rbp
0000000000000011  movq  %rsp,%rbp
0000000000000014  subq  $0x10,%rsp
0000000000000018  movl  $0x00000000,0xfc(%rbp)
000000000000001f  callq 0x00000024
0000000000000024  addq  $0x10,%rsp
0000000000000028  popq  %rbp
0000000000000029  ret
$ llvm-rtdyld t.o -debug-only=dyld ; echo $?
Function sym: '_bar' @ 0
Function sym: '_main' @ 16
Extracting function: _bar from [0, 15]
    allocated to 0x100153000
Extracting function: _main from [16, 41]
    allocated to 0x100154000
Relocation at '_main' + 16 from '_bar(Word1: 0x2d000000)
Resolving relocation at '_main' + 16 (0x100154010) from '_bar (0x100153000)(pcrel, type: 2, Size: 4).
loaded '_main' at: 0x100154000
65
$

llvm-svn: 129388

rdar://problem/9269047

llvm-svn: 129387

llvm-svn: 129385

specifier.

llvm-svn: 129384

UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make these heuristic adjustments to node latency work,
I also needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.

llvm-svn: 129383

Patch by arrowdodger!

llvm-svn: 129381