llvm-svn: 104300

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

llvm-svn: 104293

llvm-svn: 104290

llvm-svn: 104287

llvm-svn: 104279

top-level LSRInstance logic.

llvm-svn: 104278

llvm-svn: 104276

llvm-svn: 104275

llvm-svn: 104274

aren't needed.

llvm-svn: 104273

llvm-svn: 104272

llvm-svn: 104271

Changed directly instead of using a return value.

Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.

llvm-svn: 104269

llvm-svn: 104268

llvm-svn: 104267

llvm-svn: 104265

llvm-svn: 104264

llvm-svn: 104263

operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.

llvm-svn: 104262

llvm-svn: 104261

it isn't a very interesting change, it's a change nonetheless.

llvm-svn: 104260

This fixes the remaining issue with pr7167.

llvm-svn: 104257

llvm-svn: 104254

have a pattern and it had an invalid encoding.

llvm-svn: 104244

registers.  Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
 vreg = MCRF  CR0
 MFCR  <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment).  That avoids all problems.  7739628.

llvm-svn: 104238

llvm-svn: 104236

llvm-svn: 104234

Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.

llvm-svn: 104233

llvm-svn: 104232

instructions.

llvm-svn: 104231

16-bit and 32-bit pushf and popf.

llvm-svn: 104228

and fix a bug that valgrind noticed where the code would std::swap an
element with itself.

llvm-svn: 104225

llvm-svn: 104223

pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216

llvm-svn: 104209

llvm-svn: 104204

doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203

llvm-svn: 104197

the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.

llvm-svn: 104186

test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185