llvm-svn: 27336

"vspltisb v0, 8" instead of a constant pool load.

llvm-svn: 27335

multiple register classes.  This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll

llvm-svn: 27334

llvm-svn: 27333

llvm-svn: 27332

llvm-svn: 27331

llvm-svn: 27330

patch), distilled from Applications/JM/ldecod

llvm-svn: 27329

Fold (B&A)^A == ~B & A

This implements InstCombine/xor.ll:test2[56]

llvm-svn: 27328

llvm-svn: 27327

PR726 by performing consistent signed division, not consistent unsigned
division when evaluating scev's.  Do not touch udivs.

llvm-svn: 27326

llvm-svn: 27325

llvm-svn: 27324

extract_element'd value, do so.

llvm-svn: 27323

llvm-svn: 27322

llvm-svn: 27321

No functionality change.

llvm-svn: 27320

alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).

llvm-svn: 27319

llvm-svn: 27317

llvm-svn: 27316

llvm-svn: 27315

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

llvm-svn: 27313

operation.  This implements Regression/TableGen/strconcat.td.

llvm-svn: 27312

llvm-svn: 27311

llvm-svn: 27310

llvm-svn: 27309

llvm-svn: 27308

llvm-svn: 27307

llvm-svn: 27306

llvm-svn: 27305

from a 128-bit vector.

llvm-svn: 27304

llvm-svn: 27303

llvm-svn: 27302

llvm-svn: 27301

llvm-svn: 27300

Now all UnitTests/Vector/* tests pass on PPC.

llvm-svn: 27299

This fixes UnitTests/Vector/simple.c with altivec.

llvm-svn: 27298

to:

test_extract_elt:
        alloc r3 = ar.pfs,0,1,0,0
        adds r8 = 12, r32
        ;;
        ldfs f8 = [r8]
        mov ar.pfs = r3
        br.ret.sptk.many rp

instead of:

test_extract_elt:
        alloc r3 = ar.pfs,0,1,0,0
        adds r8 = 28, r32
        adds r9 = 24, r32
        adds r10 = 20, r32
        adds r11 = 16, r32
        ;;
        ldfs f6 = [r8]
        ;;
        ldfs f6 = [r9]
        adds r8 = 12, r32
        adds r9 = 8, r32
        adds r14 = 4, r32
        ;;
        ldfs f6 = [r10]
        ;;
        ldfs f6 = [r11]
        ldfs f8 = [r8]
        ;;
        ldfs f6 = [r9]
        ;;
        ldfs f6 = [r14]
        ;;
        ldfs f6 = [r32]
        mov ar.pfs = r3
        br.ret.sptk.many rp

llvm-svn: 27297

vector.ll:test_extract_elt2 into:

_test_extract_elt2:
        lfd f1, 32(r3)
        blr

instead of:

_test_extract_elt2:
        lfd f0, 56(r3)
        lfd f0, 48(r3)
        lfd f0, 40(r3)
        lfd f1, 32(r3)
        lfd f0, 24(r3)
        lfd f0, 16(r3)
        lfd f0, 8(r3)
        lfd f0, 0(r3)
        blr

llvm-svn: 27296