llvm-svn: 104232

instructions.

llvm-svn: 104231

16-bit and 32-bit pushf and popf.

llvm-svn: 104228

and fix a bug that valgrind noticed where the code would std::swap an
element with itself.

llvm-svn: 104225

llvm-svn: 104223

pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216

llvm-svn: 104209

llvm-svn: 104204

doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203

llvm-svn: 104201

llvm-svn: 104197

llvm-svn: 104196

llvm-svn: 104190

llvm-svn: 104189

the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.

llvm-svn: 104186

test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185

llvm-svn: 104183

llvm-svn: 104182

llvm-svn: 104175

more than one dbg_value instruction. rdar://7759363

llvm-svn: 104174

llvm-svn: 104173

llvm-svn: 104172

A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.

Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.

llvm-svn: 104167

llvm-svn: 104165

llvm-svn: 104163

partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149

llvm-svn: 104148

Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.

llvm-svn: 104147

lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146

llvm-svn: 104145

llvm-svn: 104143

llvm-svn: 104142

need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.

llvm-svn: 104141

llvm-svn: 104122

prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120

CALL64pcrel32, for the same reason.

llvm-svn: 104116

t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

llvm-svn: 104115

llvm-svn: 104114

llvm-svn: 104113

llvm-svn: 104112