Otherwise it will try to use SSE patterns and fail horribly if sse is disabled.
Fixes PR14035.

llvm-svn: 165377

move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351

Contributer: Vladimir Medic
llvm-svn: 165350

Contributer: Vladimir Medic
llvm-svn: 165346

into separate versions for the Darwin and 64-bit SVR4 ABIs.  This will
facilitate doing more major surgery on the 64-bit SVR4 ABI in the near future.

llvm-svn: 165336

llvm-svn: 165324

llvm-svn: 165322

llvm-svn: 165320

Implement TargetData with the DataLayout class, this will allow LLVM projects to transition to DataLayout without loosing functionality.

llvm-svn: 165318

- Mark the BCC and BLR defs as isCodeGenOnly per error output from
llvm-tblgen -gen-asm-matcher.

 PPCInstrInfo.td |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

llvm-svn: 165315

llvm-svn: 165303

Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos and mark them as pseudos in the td file.

llvm-svn: 165302

Follow up to r165072. Try a different approach: only move the load when it's going to be folded into the call. rdar://12437604

llvm-svn: 165287

segmented registers.  Test case to come.

llvm-svn: 165275

a pointer to a type, in order to remove the uses of getGlobalContext().

Patch by Tyler Nowicki.

llvm-svn: 165255

Make sure functions located in user specified text sections (via the
section attribute) are located together with the default text sections.
Otherwise, for large object files, the relocations for call instructions
are more likely to be out of range. This becomes even more likely in the
presence of LTO.

rdar://12402636

llvm-svn: 165254

a) frame setup instructions define the prologue
b) we shouldn't change our location mid-stream

Add a test to make sure that the stack adjustment stays within
the prologue.

llvm-svn: 165250

- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
  retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.

llvm-svn: 165241

- add tokens to PPCInstrInfo.td and PPCInstr64Bit.td to resolve
"Instruction 'foo' has no tokens" errors during llvm-tblgen
-gen-asm-matcher attempts.  At this time, the added
tokens are "#comment" style rather than the actual mnemonic.  This will
be revisited once the rest of the base asmparser bits get straightened
out for ppc64-elf-linux.

llvm-svn: 165237

llvm-svn: 165233

llvm-svn: 165205

macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199

This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options

    at - lets the assembler use the $at register for macros,
         but generates warnings if the source program uses $at

    noat - let source programs use $at without issuingwarnings.

    noreorder - prevents the assembler from reordering machine 
                language instructions.
    nomacro - causes the assembler to print a warning whenever 
              an assembler operation generates more than one 
              machine language instruction.
    macro - lets the assembler generate multiple machine instructions 
            from a single assembler instruction
    reorder - lets the assembler reorder machine language 
               instructions to improve performance

The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.

Following options are not implemented yet:

nomips16
nomicromips
move
nomove

Contributer: Vladimir Medic
llvm-svn: 165194

llvm-svn: 165182

in the Intel syntax.

The MC layer supports emitting in the Intel syntax, but this would require the
inline assembly MachineInstr to be lowered to an MCInst before emission.  This
is potential future work, but for now emitting directly from the MachineInstr
suffices.

llvm-svn: 165173

for the number of bytes in a particular instruction
to using
   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
   Desc.getSize()

This is necessary with the advent of 16 bit instructions with
mips16 and micromips. It is also puts Mips in compliance with
the other targets for getting instruction size.

llvm-svn: 165171

llvm-svn: 165141

enums. This allows for better encapsulation of the Attributes class.

llvm-svn: 165132

Corrects a problem whereby MCSchedModel was not being set up when
the CPU type was auto-detected.

Patch by Andy Zhang.

llvm-svn: 165122

more detail.

llvm-svn: 165099

llvm-svn: 165089

Enable the pass by default for targets that request it, and change the
-enable-early-ifcvt to the opposite -disable-early-ifcvt.

There are still some x86 regressions when enabling early if-conversion
because of the missing machine models. Disable the pass for x86 until
machine models are added.

llvm-svn: 165075

X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside
callseq_start / callseq_end so it can be folded into a call. This can
create a cycle in the DAG when the call is glued to a copytoreg. We
have been lucky this hasn't caused too many issues because the pre-ra
scheduler has special handling of call sequences. However, it has
caused a crash in a specific tailcall case.

rdar://12393897

llvm-svn: 165072

This reverts 165055 and 165052 temporarily while I look at debugger
failures.

llvm-svn: 165071

llvm-svn: 165069

The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands.

If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler.

This code was originally called from  MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically.

The test cases have been checked in for a number of weeks now.

llvm-svn: 165067

llvm-svn: 165063

of operand is specific to MS-style inline assembly and should not be generated
when parsing normal assembly.

The purpose of the wildcard operands are to allow the AsmParser to match
multiple instructions (i.e., MCInsts) to a given ms-style asm statement.  For
the time being the matcher just returns the first match.  This patch only
implements wildcard matches for memory operands.  Support for register
wildcards will be added in the near future.

llvm-svn: 165057

prologue. Also skip frame setup instructions when looking for the
first location.

llvm-svn: 165052

llvm-svn: 165051