redundant after the change.

llvm-svn: 23759

SelectNodeTo instead of getTargetNode when possible.

llvm-svn: 23758

This still doesn't talk about autogen much

llvm-svn: 23757

llvm-svn: 23756

llvm-svn: 23755

llvm-svn: 23754

SelectIntImmediateExpr dead.

llvm-svn: 23753

llvm-svn: 23752

llvm-svn: 23751

llvm-svn: 23750

llvm-svn: 23749

a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction.  This allows FMA32
patterns to not match double expressions for example.

llvm-svn: 23748

fixes a legalize failure on SPASS for itanium.

llvm-svn: 23747

llvm-svn: 23746

This completes the grand PPC file renaming

llvm-svn: 23745

and PPC32JITInfo classes should be merged.

llvm-svn: 23744

llvm-svn: 23743

llvm-svn: 23742

still should be merged into the PPC32TargetMachine class

llvm-svn: 23741

llvm-svn: 23740

llvm-svn: 23739

llvm-svn: 23738

llvm-svn: 23737

from the .td file that correspond to it

llvm-svn: 23736

fixing a bunch of nasty hackery

llvm-svn: 23735

We will decide with subtarget support whether we ever use an i64 register
class.

llvm-svn: 23734

llvm-svn: 23733

llvm-svn: 23732

llvm-svn: 23731

type constraint.  This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.

llvm-svn: 23730

Overall, no functionality change yet though.

llvm-svn: 23729

llvm-svn: 23728

llvm-svn: 23727

llvm-svn: 23726

llvm-svn: 23725

1. If an operation has to be int or fp and the target only supports one
   int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
   for patterns involving those operators, since we do not emit the code to
   check for them yet.  This prevents PPC from generating FP ops currently.

Also move some code around into more logical places.

llvm-svn: 23724

llvm-svn: 23723

popping up in Fourinarow.

llvm-svn: 23722

llvm-svn: 23721

you could be AND'ing with the result of a shift that shifts out all the
bits you care about, in addition to a constant.

Also, move over an add/sub_parts fold from legalize to the dag combiner,
where it works for things other than constants.  Woot!

llvm-svn: 23720