llvm-svn: 122572

llvm-svn: 122571

llvm-svn: 122570

llvm-svn: 122568

llvm-svn: 122567

llvm-svn: 122566

llvm-svn: 122565

llvm-svn: 122563

No functionality yet.

llvm-svn: 122562

llvm-svn: 122561

llvm-svn: 122560

llvm-svn: 122559

rejected by the mc assembler.

llvm-svn: 122557

llvm-svn: 122556

getOrEnforceKnownAlignment function, which simplifies the code
and makes it stronger.

llvm-svn: 122555

llvm-svn: 122554

llvm-svn: 122553

llvm-svn: 122551

Fix a thinko pointed out by Frits van Bommel: looking through global variables in isBytewiseValue is not safe.

llvm-svn: 122550

have a single point where targets test if a relocation is needed.

llvm-svn: 122549

This allows us to compile "int cst[] = {-1, -1, -1};" into
  movl  $-1, 16(%rsp)
  movq  $-1, 8(%rsp)
instead of
  movl  _cst+8(%rip), %eax
  movl  %eax, 16(%rsp)
  movq  _cst(%rip), %rax
  movq  %rax, 8(%rsp)

llvm-svn: 122548

llvm-svn: 122547

llvm-svn: 122545

Fix a few cases where the scheduler is not checking for phys reg copies. The scheduling node may have a NULL DAG node, yuck.

llvm-svn: 122544

llvm-svn: 122542

DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

llvm-svn: 122541

llvm-svn: 122539

llvm-svn: 122537

preprocessed .s files and matches darwin gas.  rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.

llvm-svn: 122531

llvm-svn: 122530

are not the low bits of x, but the bits that WILL be the low bits after the operation completes.

llvm-svn: 122529

llvm-svn: 122528

llvm-svn: 122524

llvm-svn: 122523

If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.

llvm-svn: 122521

It was causing problems on the MinGW build. See PR8849.

llvm-svn: 122518

llvm-svn: 122517

pipeline to be caught by instcombine, and it's not feasible to catch them in SimplifyCFG because the
use-lists are in an inconsistent state at the point where it could know that it need to simplify them.
Instead, have CodeGenPrepare look for trivially redundant PHIs as part of its general cleanup effort.

llvm-svn: 122516

llvm-svn: 122513

llvm-svn: 122509