llvm-svn: 139069

duplicate it for AVX mode.

llvm-svn: 139068

llvm-svn: 139067

that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066

pattern should be matched

llvm-svn: 139065

llvm-svn: 139064

it!

llvm-svn: 139063

llvm-svn: 139062

llvm-svn: 139061

OptForSize pattern

llvm-svn: 139060

If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert.  The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users.  No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.

llvm-svn: 139059

llvm-svn: 139058

The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057

It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056

llvm-svn: 139055

llvm-svn: 139054

llvm-svn: 139053

llvm-svn: 139052

llvm-svn: 139051

llvm-svn: 139050

Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049

llvm-svn: 139048

llvm-svn: 139047

llvm-svn: 139046

llvm-svn: 139044

llvm-svn: 139043

llvm-svn: 139042

// rdar://10033896

llvm-svn: 139041

For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040

llvm-svn: 139039

llvm-svn: 139038

llvm-svn: 139037

llvm-svn: 139036

slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.

llvm-svn: 139035

Add a virtual method GetHardwareWatchpointHit() to the DNBArchProtocol base class
which consults the architecture to return the watchpoint hit; otherwise return an
invalid index.

Add impl. of the method to X86_64 and I386 subclasses, plus reset the debug status
register before we resume execution of the inferior thread.

llvm-svn: 139034

llvm-svn: 139033

llvm-svn: 139032

Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names.  We'll use this to
provide more programmability in how we name defs and their associated
members.

llvm-svn: 139031

llvm-svn: 139029

case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028