us to compile stuff like this:

double %test(double %A, double %B, double %C, double %E) {
        %F = mul double %A, %A
        %G = add double %F, %B
        %H = sub double -0.0, %G
        %I = mul double %H, %C
        %J = add double %I, %E
        ret double %J
}

to:

_test:
        fnmadd f0, f1, f1, f2
        fmadd f1, f0, f3, f4
        blr

woot!

llvm-svn: 22937

llvm-svn: 22936

llvm-svn: 22935

llvm-svn: 22934

This gets us this for the previous testcase:

_test:
        lis r2, 0
        ori r3, r2, 65535
        blr

Note that we actually write to r3 (the return reg) correctly now :)

llvm-svn: 22933

temporary registers for things that define a register.  This allows dag->dag
isel to compile this:

int %test() { ret int 65535 }

into:

_test:
        lis r2, 0
        ori r2, r2, 65535
        blr

Next up, getting CopyFromReg to work, allowing arguments and cross-bb values.

llvm-svn: 22932

Emit this:

static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };

For operand information, which does not require dynamic (startup-time)
initialization.

llvm-svn: 22931

to be accessed.

llvm-svn: 22930

llvm-svn: 22929

llvm-svn: 22928

llvm-svn: 22927

llvm-svn: 22926

llvm-svn: 22925

llvm-svn: 22924

namespace instead of the reg class namespace.  Update getRegClassForType()
to use modified names due to tblgen change.

llvm-svn: 22923

llvm-svn: 22922

llvm-svn: 22921

anonymous regclass definition renaming.

Change the generated code to emit register classes as properly namespace
qualified entities like everything else.

expose the actual class definition as an object, though this isn't quite
usable yet.

llvm-svn: 22920

in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919

llvm-svn: 22918

llvm-svn: 22917

llvm-svn: 22916

llvm-svn: 22915

llvm-svn: 22914

llvm-svn: 22913

llvm-svn: 22912

llvm-svn: 22911

llvm-svn: 22910

llvm-svn: 22909

operands.

llvm-svn: 22908

llvm-svn: 22907

llvm-svn: 22905

(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.

llvm-svn: 22904

llvm-svn: 22903

llvm-svn: 22902

instruction.

llvm-svn: 22901

llvm-svn: 22900

llvm-svn: 22899

llvm-svn: 22898

words.  There is no way for one of these targets to have a > 32-bit immediate!

llvm-svn: 22897