It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.

llvm-svn: 128688

The LocalStackSlotAllocation pass was creating illegal registers.

llvm-svn: 128687

llvm-svn: 128686

llvm-svn: 128685

llvm-svn: 128683

__block block declaration. //rdar://9204669

llvm-svn: 128682

Note this can potentially be enhanced to detect if the __block variable
is actually written by the block, or only when the block "escapes" or
is actually used, but that requires more analysis than it is probably worth
for this simple check.

llvm-svn: 128681

llvm-svn: 128680

Add security syntax checker for strcpy() which causes the Static Analyzer to generate a warning any time the strcpy() function is used with a note suggesting to use a function which provides bounded buffers. 

llvm-svn: 128679

llvm-svn: 128678

Models mempcpy() so that if length is NULL the destination pointer is returned. Otherwise, the source and destination are confirmed not to be NULL and not overlapping. Finally the copy is validated to not cause a buffer overrun and the return value is bound to the address of the byte after the last byte copied.

llvm-svn: 128677

Thanks Eli!

llvm-svn: 128676

Fix a few typos in the previous commit.

llvm-svn: 128671

llvm-svn: 128670

Add code to emulate VLD1 (single element to all lanes) ARM instruction.

llvm-svn: 128669

amounts to an UNDEFINED instruction.

llvm-svn: 128668

accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

llvm-svn: 128665

Make ChainedIncludesSource an ExternalSemaSource, otherwise initialization of the ASTReader is incomplete, leading to errors like not realizing std::type_info is already defined.

llvm-svn: 128664

Tell the diagnostic client about starting and ending source files when automatically creating chained PCHs. This way, we don't get a crash whenever a diagnostic is emitted while processing the include.

llvm-svn: 128663

Inst{4} = 0.

rdar://problem/9213022

llvm-svn: 128662

Add code to emulate VST1 (single element from one lane) ARM
instruction (more floating point stores).

llvm-svn: 128661

Add code to emulate VST1 (multiple single elements) ARM
instruction (floating point store).

llvm-svn: 128656

Add an extra run with -regalloc=basic to keep them honest.

llvm-svn: 128654

llvm-svn: 128650

isn't an exact float. Also "fpext float 1.0 to float" is invalid IR because
it's not performing an extension.

llvm-svn: 128647

Add code to emulate VLD1 (single element to one lane) floating point
register load instruction (ARM) .

llvm-svn: 128646

Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.

llvm-svn: 128645

A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644

llvm-svn: 128643

This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.

llvm-svn: 128642

llvm-svn: 128641

llvm-svn: 128640

llvm-svn: 128639

Revert changes that caused this scheme to be hidden in certain cases.

llvm-svn: 128638

Add code to emulate VLD1 (multiple single elements) ARM instruction.

llvm-svn: 128637

llvm-svn: 128636

llvm-svn: 128635

llvm-svn: 128634

llvm-svn: 128633

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632