llvm-svn: 156102

llvm-svn: 156084

Many register classes only have a few super-registers, so it is not
necessary to keep individual bit masks for all possible sub-register
indices.

llvm-svn: 156083

llvm-svn: 156080

llvm-svn: 156077

Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.

llvm-svn: 156075

This adds new instructions for Hexagon V4 architecture.

llvm-svn: 156071

replace 'break's with 'return 0' in visitCallInst code for objectsize, since there is no need to fallback to visitCallSite.
This gives a 0.9% in a test case

llvm-svn: 156069

llvm-svn: 156067

llvm-svn: 156060

Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982.

llvm-svn: 156059

to catch cases like:
 %reg1024<def> = MOV r1
 %reg1025<def> = MOV r0
 %reg1026<def> = ADD %reg1024, %reg1025
 r0            = MOV %reg1026

By commuting ADD, it let coalescer eliminate all of the copies. However, there
was a bug in the heuristics where it ended up commuting the ADD in:

 %reg1024<def> = MOV r0
 %reg1025<def> = MOV 0
 %reg1026<def> = ADD %reg1024, %reg1025
 r0            = MOV %reg1026

That did no benefit but rather ensure the last MOV would not be coalesced.

rdar://11355268

llvm-svn: 156048

The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.

This ensures that targets define register classes as intended.

llvm-svn: 156046

llvm-svn: 156034

llvm-svn: 156032

Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs.

llvm-svn: 156029

For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.

llvm-svn: 156028

Lincroft and Medfield.

llvm-svn: 156025

llvm-svn: 156023

llvm-svn: 156021

llvm-svn: 156019

be used by clang-tblgen.

llvm-svn: 156000

This avoids warnings when included in a application that
uses -Wstrict-prototypes. 

e.g: AsmPrinters.def:27:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]

llvm-svn: 155997

by providing the latencies for the instructions in X86InstrFPStack.td.

llvm-svn: 155996

The commit is intended to fix rdar://10961709.
But it is the root cause of PR12720.
Revert it for now.

llvm-svn: 155992

llvm-svn: 155986

methods. Use a weak value handle to keep up with this.
PR12245

llvm-svn: 155984

llvm-svn: 155983

llvm-svn: 155982

Note that support for rvalue references does not imply support
for the full set of move-related STL operations.

I've preserved support for an odd little thing in insert() where
we're trying to support inserting a new element from an existing
one.  If we actually want to support that, there's a lot more we
need to do:  insert can call either grow or push_back, neither of
which is safe against this particular use pattern.

llvm-svn: 155979

llvm-svn: 155978

llvm-svn: 155976

llvm-svn: 155960

llvm-svn: 155959

llvm-svn: 155957

llvm-svn: 155956

PR10799

llvm-svn: 155954

llvm-svn: 155947

Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
        adds.w r2, #-16
        adds.w r2, r2, #-16
        addw r2, #-16
        addw r2, #-16
        addw r2, r2, #-16

rdar://11330769

llvm-svn: 155946

Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.

rdar://10550147

llvm-svn: 155941