- Jun 09, 2012
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Jakob Stoklund Olesen authored
The fast register allocator is not supposed to work in the optimizing pipeline. It doesn't make sense to compute live intervals, run full copy coalescing, and then run RAFast. Fast register allocation in the optimizing pipeline is better done by RABasic. llvm-svn: 158242
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Nuno Lopes authored
-%a + 42 into 42 - %a previously we were emitting: -(%a + 42) This fixes the infinite loop in PR12338. The generated code is still not perfect, though. Will work on that next llvm-svn: 158237
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- Jun 08, 2012
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Evan Cheng authored
llvm-svn: 158234
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Andrew Trick authored
llvm-svn: 158233
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Duncan Sands authored
problem was that by moving instructions around inside the function, the pass could accidentally move the iterator being used to advance over the function too. Fix this by only processing the instruction equal to the iterator, and leaving processing of instructions that might not be equal to the iterator to later (later = after traversing the basic block; it could also wait until after traversing the entire function, but this might make the sets quite big). Original commit message: Grab-bag of reassociate tweaks. Unify handling of dead instructions and instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. llvm-svn: 158226
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Hal Finkel authored
As Chris points out, this can now be removed! TODO: check if the associated section on viterbi's inner loop can also be removed. llvm-svn: 158224
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Hal Finkel authored
Thanks to Jakob's help, this now causes no new test suite failures! Over the entire test suite, this gives an average 1% speedup. The largest speedups are: SingleSource/Benchmarks/Misc/pi - 108% SingleSource/Benchmarks/CoyoteBench/lpbench - 54% MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50% SingleSource/Benchmarks/Shootout/ary3 - 32% SingleSource/Benchmarks/Shootout-C++/matrix - 30% The largest slowdowns are: MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30% MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22% MultiSource/Applications/d/make_dparser - -14% SingleSource/Benchmarks/Shootout-C++/ary - -13% In light of these slowdowns, additional profiling work is obviously needed! llvm-svn: 158223
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Hal Finkel authored
Marking these classes as non-alocatable allows CTR loop generation to work correctly with the block placement passes, etc. These register classes are currently used only by some unused TCRETURN patterns. In future cleanup, these will be removed. Thanks again to Jakob for suggesting this fix to the CTR loop problem! llvm-svn: 158221
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Manman Ren authored
llvm-svn: 158220
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Manman Ren authored
llvm-svn: 158218
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Andrew Trick authored
This fixes an accidental dependence on static initialization order that I introduced yesterday. Thank you Lang!!! llvm-svn: 158215
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Chad Rosier authored
Patch by James Benton <jbenton@vmware.com>. llvm-svn: 158213
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Andrew Trick authored
Bulk move of TargetInstrInfo implementation into TargetInstrInfoImpl. This is dirty because the code isn't part of TargetInstrInfoImpl class, nor should it be, because the methods are not target hooks. However, it's the current mechanism for keeping libTarget useful outside the backend. You'll get a not-so-nice link error if you invoke a TargetInstrInfo method that depends on CodeGen. The TargetInstrInfoImpl class should probably be removed since it doesn't really solve this problem. To really fix this, we probably need separate interfaces for the CodeGen/nonCodeGen sides of TargetInstrInfo. llvm-svn: 158212
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Nuno Lopes authored
BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrumentation failures in loops with reallocs llvm-svn: 158210
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NAKAMURA Takumi authored
llvm-svn: 158209
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Hal Finkel authored
The pass itself works well, but the something in the Machine* infrastructure does not understand terminators which define registers. Without the ability to use the block-placement pass, etc. this causes performance regressions (and so is turned off by default). Turning off the analysis turns off the problems with the Machine* infrastructure. llvm-svn: 158206
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Hal Finkel authored
The code which tests for an induction operation cannot assume that any ADDI instruction will have a register operand because the operand could also be a frame index; for example: %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16 llvm-svn: 158205
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Hal Finkel authored
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. llvm-svn: 158204
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Duncan Sands authored
can move instructions within the instruction list. If the instruction just happens to be the one the basic block iterator is pointing to, and it is moved to a different basic block, then we get into an infinite loop due to the iterator running off the end of the basic block (for some reason this doesn't fire any assertions). Original commit message: Grab-bag of reassociate tweaks. Unify handling of dead instructions and instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. llvm-svn: 158199
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Tobias Grosser authored
This was previously only done for executables and shared libraries, but not for modules. As modules are essentially shared libraries (that need to be dlopened explicitly), threating them the same as shared libraries seems reasonable. This fixes the LLVM_BUILD_32_BITS build of Polly. Contributed by: Ondra Hosek <ondra.hosek@gmail.com> llvm-svn: 158195
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Owen Anderson authored
Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string. llvm-svn: 158183
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Michael J. Spencer authored
llvm-svn: 158176
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Manman Ren authored
This patch will generate the following for integer ABS: movl %edi, %eax negl %eax cmovll %edi, %eax INSTEAD OF movl %edi, %ecx sarl $31, %ecx leal (%rdi,%rcx), %eax xorl %ecx, %eax There exists a target-independent DAG combine for integer ABS, which converts integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. This is implemented in PerformXorCombine. rdar://10695237 llvm-svn: 158175
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- Jun 07, 2012
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Michael J. Spencer authored
llvm-svn: 158171
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Michael J. Spencer authored
Remove /Wall from LLVM_ENABLE_WARNINGS (it's useless) and promote 4239 to a level 1 warning. llvm-svn: 158170
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Nadav Rotem authored
Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates. This may happen on MIC devices. llvm-svn: 158168
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Nadav Rotem authored
Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elements, which may disagree with the select condition type. llvm-svn: 158166
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Andrew Trick authored
llvm-svn: 158164
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Andrew Trick authored
Match expectations of the new latency API. Cleanup and make the logic consistent. llvm-svn: 158163
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Andrew Trick authored
llvm-svn: 158162
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Andrew Trick authored
llvm-svn: 158161
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Manman Ren authored
It will cause assertion failure later on. llvm-svn: 158160
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Rafael Espindola authored
Fixes pr13048. llvm-svn: 158158
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Pete Cooper authored
Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator llvm-svn: 158154
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Pete Cooper authored
Add internal read flags to MachineInstrBuilder and hook them into the MachineOperand flag of the same name llvm-svn: 158137
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Meador Inge authored
llvm-svn: 158128
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Manman Ren authored
This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 llvm-svn: 158126
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Bill Wendling authored
llvm-svn: 158123
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Manman Ren authored
The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. llvm-svn: 158122
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Bill Wendling authored
<rdar://problem/10889741> llvm-svn: 158121
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