Fix multiclass inheritance to limit value resolution to new defs added
by base multiclasses.  Do not attempt to alter defs from previous base
multiclasses.  This fixes multiple multiclass inheritance.

llvm-svn: 69974

Make BinOps typed and require a type specifier for !nameconcat.  This
allows binops to be used in typed contexts such as when passing
arguments to classes.

llvm-svn: 69921

Implement !nameconcat to concatenate strings and look up the resulting
name in the symbol table, returning an object.

llvm-svn: 69822

in selectiondag patterns.  This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.

llvm-svn: 67286

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

llvm-svn: 52177

llvm-svn: 45419

print in terms of that.

llvm-svn: 44276

llvm-svn: 44275

llvm-svn: 44257

llvm-svn: 43993

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 37063

llvm-svn: 34697

CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
It's missing CallingConvEmitter.h

llvm-svn: 34693

llvm-svn: 34682

llvm-svn: 32333

Remove unused variables.

llvm-svn: 31381

operation.  This implements Regression/TableGen/strconcat.td.

llvm-svn: 27312

llvm-svn: 27263

llvm-svn: 26287

llvm-svn: 25836

llvm-svn: 25014

llvm-svn: 24540

reflect what it is.
Convert some more code over to use it.

llvm-svn: 24072

simplifies using list of records.

llvm-svn: 24069

methods.  Use it to simplify some code.

llvm-svn: 23336

llvm-svn: 22911

llvm-svn: 21441

llvm-svn: 21428

llvm-svn: 21361

finished up, only resolve fully when the def is defined.  This allows things
to be changed and all uses to be propagated through.  This implements
TableGen/LazyChange.td and fixes TemplateArgRename.td in the process.

None of the .td files used in LLVM backends are changed at all by this
patch.

llvm-svn: 21344

llvm-svn: 21336

llvm-svn: 17484

llvm-svn: 16838

llvm-svn: 16616

llvm-svn: 15381

llvm-svn: 15249

like this:

def B {
  list<int> X = [10, 20, 30, 4, 1, 1231, 20] [2-4,2,2,0-6];
}

... which isn't particularly useful, but more is to come.

llvm-svn: 15247

llvm-svn: 14291