revision id is appended to the LLVM version string. Defaults to
OFF.

Until now the VC revision id was always appended to the revision
string whenever cmake was invoked (either explicitly or implicitly
because a cmake source file changed). This was causing massive
recompilations because config.h are reconfigured with the new contents
of PACKAGE_VERSION.

llvm-svn: 122240

llvm-svn: 122239

llvm-svn: 122238

llvm-svn: 122237

to make sure that the reused alloca has sufficient alignment.

llvm-svn: 122236

llvm-svn: 122235

argument.  The generated alloca has to have at least the alignment of the
byval, if not, the client may be making assumptions that the new alloca won't
satisfy.

llvm-svn: 122234

llvm-svn: 122233

llvm-svn: 122232

Remove a line: this test is line position sensitive.

llvm-svn: 122231

llvm-svn: 122230

XFAIL for now, I'll investigate why later.

llvm-svn: 122229

out-edges. Fixes PR8824.

llvm-svn: 122228

I have no idea how to fix it.

llvm-svn: 122227

llvm-svn: 122226

begin at DEF slots. Fixes the second half of PR8813.

llvm-svn: 122225

llvm-svn: 122224

pack expansions, e.g. given

  template<typename... Types> struct tuple;

  template<typename... Types>
  struct tuple_of_refs {
    typedef tuple<Types&...> types;
  };

the type of the "types" typedef is a PackExpansionType whose pattern
is Types&. 

This commit introduces support for creating pack expansions for
template type arguments, as above, but not for any other kind of pack
expansion, nor for any form of instantiation.

llvm-svn: 122223

llvm-svn: 122222

ARM (and other 32-bit-only) targets support for i8 and i16 overflow 
multiplies.  The generated code isn't great, but this at least fixes
CodeGen/Generic/overflow.ll when running on ARM hosts.

llvm-svn: 122221

llvm-svn: 122220

the same as setcc.  Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS).  This is
a step towards finishing off PR5443.  In the testcase in that bug we now  get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbq	%rcx, %rcx
	testb	$1, %cl
	setne	%dl
	ret

instead of:

	movq	%rdi, %rax
	addq	%rsi, %rax
	movl	$0, %ecx
	adcq	$0, %rcx
	testq	%rcx, %rcx
	setne	%dl
	ret

llvm-svn: 122219

the register; it may be a dead def instead. Fixes PR8820.

llvm-svn: 122218

doesn't, match it back to setb.

On a 64-bit version of the testcase before we'd get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbb	%dl, %dl
	andb	$1, %dl
	ret

now we get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	setb	%dl
	ret

llvm-svn: 122217

llvm-svn: 122216

llvm-svn: 122215

llvm-svn: 122214

their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.

We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.

With the previous series of changes, this causes no changes in the testsuite, woo.

llvm-svn: 122213

llvm-svn: 122212

Imagine we see:

EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS

Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor.  However, it also uses the EFLAGS
of the predecessor, so it is safe to emit.  SDep edges ensure that
the right order happens already anyway.

This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.

llvm-svn: 122211

llvm-svn: 122210

llvm-svn: 122209

llvm-svn: 122208

PR8822.

llvm-svn: 122207

has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.

llvm-svn: 122206

half of PR8813.

llvm-svn: 122205

llvm-svn: 122204

llvm-svn: 122203

ConnectedVNInfoEqClasses::Classify().

llvm-svn: 122202

consistently by moving it out of lowering into dag combine.

Add some missing patterns for matching away extended versions of setcc_c.

llvm-svn: 122201