[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.

llvm-svn: 191167

[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.

llvm-svn: 191166

llvm-svn: 183243

Test case by llvm-stress.

llvm-svn: 179477

SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

llvm-svn: 178525

Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

llvm-svn: 150878

llvm-svn: 45418

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 30039

llvm-svn: 25985

InstV8 class to the InstrFormats file where it belongs.

llvm-svn: 24824

to a bug in the scheduler.

llvm-svn: 24807

llvm-svn: 24800

llvm-svn: 24779

llvm-svn: 24776

llvm-svn: 24771

minor bugs

llvm-svn: 24762

programs to work on V8 again

llvm-svn: 24761

llvm-svn: 24744

llvm-svn: 24741

llvm-svn: 24740

With this, Regression/CodeGen/SparcV8/basictest.ll now passes.  Lets hear it
for regression tests :)

llvm-svn: 24738

llvm-svn: 17001

* In the F3_3 class, remove mention of asi because it's not part of the format

llvm-svn: 16999

llvm-svn: 16484

Replace it with a working class for FP instrs.

llvm-svn: 14226

llvm-svn: 11957

llvm-svn: 11955

llvm-svn: 11832