llvm-svn: 104731

llvm-svn: 104713

llvm-svn: 104711

before encoding.

llvm-svn: 104707

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

llvm-svn: 104699

llvm-svn: 104697

llvm-svn: 104696

llvm-svn: 104691

llvm-svn: 104670

Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667

llvm-svn: 104661

This reverts commit 104654.

llvm-svn: 104660

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653

Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652

llvm-svn: 104650

are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.

llvm-svn: 104634

llvm-svn: 104629

llvm-svn: 104628

SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627

llvm-svn: 104626

llvm-svn: 104622

for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621

Fixes rdar://8017638

llvm-svn: 104617

This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615

llvm-svn: 104612

The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

llvm-svn: 104611

Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))

llvm-svn: 104588

llvm-svn: 104587

I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.

llvm-svn: 104583

Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.

llvm-svn: 104582

llvm-svn: 104580

llvm-svn: 104573

llvm-svn: 104571

version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570

llvm-svn: 104564

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

llvm-svn: 104552

llvm-svn: 104549