INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726

This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725

llvm-svn: 107723

llvm-svn: 107721

llvm-svn: 107720

llvm-svn: 107717

Update VEX encoding to support those new instructions

llvm-svn: 107715

SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712

llvm-svn: 107710

llvm-svn: 107701

llvm-svn: 107700

llvm-svn: 107699

llvm-svn: 107698

llvm-svn: 107697

llvm-svn: 107696

It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.

This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.

llvm-svn: 107695

the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691

Patch from Roman Divacky.

llvm-svn: 107688

Binary Interface specification.

llvm-svn: 107685

llvm-svn: 107684

and give a more precise return type for some of the type-creation methods.

llvm-svn: 107683

llvm-svn: 107680

llvm-svn: 107678

an IRBuilder.

llvm-svn: 107677

if profitable.

llvm-svn: 107673

llvm-svn: 107670

Patch by Kenneth Hoste.

llvm-svn: 107669

llvm-svn: 107668

making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.


I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

llvm-svn: 107667

which do not depend on SelectionDAG.

llvm-svn: 107666

should be used for.

llvm-svn: 107661

from getPhysicalRegisterRegClass.

llvm-svn: 107660

clarify a few other things.

llvm-svn: 107659

Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards.
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').

llvm-svn: 107658

llvm-svn: 107657

llvm-svn: 107656

the pseudo instruction is not at the end of the block.

llvm-svn: 107655

llvm-svn: 107641

registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.

llvm-svn: 107640

llvm-svn: 107637