Overriding doFinalization is pretty lame.

llvm-svn: 82268

move a SUBFC (etc.) below the SUBFE (etc.) that consumed
the carry bit.  Add missing ADDIC8, noticed along the way.

llvm-svn: 82266

on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.

llvm-svn: 82263

carry bit) instructions to the Intel instruction
tables.

llvm-svn: 82260

llvm-svn: 82259

Update malloc call creation code (AllocType is now the element type of the malloc, not the resulting type).

In getMallocArraySize(), fix bug in the case that array size is the product of 2 constants.

Extend isArrayMalloc() and getMallocArraySize() to handle case where malloc is used as char array.

Ensure that ArraySize in LowerAllocations::runOnBasicBlock() is correct type.

Extend Instruction::isSafeToSpeculativelyExecute() to handle malloc calls.

Add verification for malloc calls.

Reviewed by Dan Gohman.

llvm-svn: 82257

llvm-svn: 82245

llvm-svn: 82235

variables to specified absolute address. Make use of this feature for MSP430.
This unbreaks PR4776.

llvm-svn: 82227

llvm-svn: 82225

llvm-svn: 82215

Fix a bug in sdisel switch lowering code. When it updates the phi nodes in switch successor blocks, it can introduce multiple phi operands of the same value from different blocks (and may not be on the predecessor list).

This can be seen on CodeGen/Generic/2006-09-06-SwitchLowering.ll. But it's not known to cause any real regression (but I have added an assertion for it now).

llvm-svn: 82214

llvm-svn: 82206

64-bit systems.

llvm-svn: 82180

llvm-svn: 82175

currently unused.

llvm-svn: 82157

where the induction variable has a non-unit stride, such as {0,+,2}, and
there are expressions such as {1,+,2} inside the loop formed with
or or add nsw operators.

llvm-svn: 82151

llvm-svn: 82150

llvm-svn: 82145

llvm-svn: 82127

llvm-svn: 82110

Fix PR4910: Broken logic in coalescer means when a physical register liveness is being shortened, the sub-registers were not. The symptom is the register allocator could not find a free register for this particular test. 

llvm-svn: 82108

llvm-svn: 82100

llvm-svn: 82097

as part string parsing) instructions to the Intel
instruction tables.

llvm-svn: 82089

llvm-svn: 82087

instructions to the Intel instruction tables.

llvm-svn: 82084

instruction tables.

llvm-svn: 82083

to the Intel instruction tables.

llvm-svn: 82081

llvm-svn: 82080

llvm-svn: 82077

constants out of loops. These aren't covered by the regular LICM
pass, because in LLVM IR constants don't require separate
instructions. They're not always covered by the MachineLICM pass
either, because it doesn't know how to unfold folded constant-pool
loads. This is somewhat experimental at this point, and off by
default.

llvm-svn: 82076

llvm-svn: 82075

llvm-svn: 82074

llvm-svn: 82064

llvm-svn: 82063

This interface will be used to attach metadata with an instruction.

llvm-svn: 82060

llvm-svn: 82054

phis, similar to the FoldPHIArgGEPIntoPHI change.

Also, delete some comments that don't reflect the code.

llvm-svn: 82053

failures.

llvm-svn: 82040