llvm-svn: 191423

llvm-svn: 191422

llvm-svn: 191421

llvm-svn: 191420

Encodings were checked against the Power ISA documents and double
checked against binutils.

This fixes PR17350.

llvm-svn: 191419

template and defined outside it, don't instantiate it twice when instantiating
the surrounding class template specialization. That would cause us to reject
the code because we think two partial specializations instantiated to produce
the same signature.

llvm-svn: 191418

yet approved by full committee, but was unanimously supported by EWG.

llvm-svn: 191417

llvm-svn: 191416

This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida

llvm-svn: 191415

[mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
 
Internal changes only.
 
Patch by Matheus Almeida

llvm-svn: 191414

 
Patch by Matheus Almeida

llvm-svn: 191413

In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida

llvm-svn: 191412

[mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
 
This only changes internal encodings and doesn't affect output.


Patch by Matheus Almeida

llvm-svn: 191411

Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
  x = a + b (add)
  y = a * x (mul)
  z = y + b * y (mla)

Without distribution:
  x = a + b (add)
  z = x * x (mul)

This patch checks if a mul is a square of add/sub. If yes, skip
distribution.

llvm-svn: 191410

Argument spelling feedback welcome.

llvm-svn: 191409

llvm-svn: 191408

llvm-svn: 191407

These symbols were showing up as undefined when trying to link programs on
Android. We should match libgcc's behaviour and provide inline definitions
of these on ARM.

It seems unwind.h on ARM/Darwin doesn't provide inline definitions, so we
just declare them for that platform.

llvm-svn: 191406

llvm-svn: 191405

llvm-svn: 191404

llvm-svn: 191403

llvm-svn: 191402

llvm-svn: 191401

and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.

llvm-svn: 191400

Changed fuzz tests to not print their values (we only need to test if access to them does not crash).
This fixes the 'No value' string appearing in the dotest results.

llvm-svn: 191399

llvm-svn: 191398

libsupc++ in typeinfo.cpp, bringing it into agreement with
exception.cpp. This fixes link errors due to duplicate symbols from
this translation unit.

llvm-svn: 191397

- to verify that r191392 has the desired effect

llvm-svn: 191396

declared in a typedef declaraton used as super
class of an ObjC class. Curretnly, these protocols
are dropped from the class hierarchy. Test shows that
it is now included. // rdar://15051465

llvm-svn: 191395

llvm-svn: 191394

 (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).

The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.

This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.

llvm-svn: 191393

el_gets was using fflush to output it's string, but because we have our own filter running on the piped pty output, fflush only causes the prompt to be written into the pipe, and does not cause the filter code to run immediately.

The simplest fix is to manually block and wait for all editline output to be processed.

This fixes PR 14637.

llvm-svn: 191392

Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

llvm-svn: 191391

llvm-svn: 191390

llvm-svn: 191389

llvm-svn: 191388

llvm-svn: 191387

At least on NetBSD, none of the already included headers pulls it in.

llvm-svn: 191386

otherwise -Werror builds may fail.

llvm-svn: 191385

sys/param.h.

llvm-svn: 191384