Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.

llvm-svn: 72894

using Promote which won't work because i64 isn't
a legal type.  It's easy enough to use Custom, but
then we have the problem that when the type
legalizer is promoting FP_TO_UINT->i16, it has no
way of telling it should prefer FP_TO_SINT->i32
to FP_TO_UINT->i32.  I have uncomfortably hacked
this by making the type legalizer choose FP_TO_SINT
when both are Custom.
This fixes several regressions in the testsuite.

llvm-svn: 72891

llvm-svn: 72866

llvm-svn: 72861

the code tried to use "push", which doesn't exist for XMM registers.)

llvm-svn: 72836

llvm-svn: 72830

Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.

llvm-svn: 72826

llvm-svn: 72817

llvm-svn: 72808

For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.

I view this as a temporary workaround until the assembler / linker changes.

llvm-svn: 72806

carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This
eliminates the need for them to search through the
MachineRegisterInfo livein list in order to identify these
virtual registers. EmitLiveInCopies is now the only user of the
virtual register portion of MachineRegisterInfo's livein data.

llvm-svn: 72802

with an accessor method which simply casts the parent class
SelectionDAGISel's TM to the target-specific type.

llvm-svn: 72801

that puts a new warning in).

llvm-svn: 72797

llvm-svn: 72782

Emit file directives correctly in case of a .bc is generated by llvm-ld after linking in several .bc files.

llvm-svn: 72781

Expand it exactly like GlobalAddress.
Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs.

llvm-svn: 72776

llvm-svn: 72771

this function" when using a not-too-smart compiler.

llvm-svn: 72768

llvm-svn: 72757

llvm-svn: 72756

relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.

llvm-svn: 72746

llvm-svn: 72734

llvm-svn: 72712

llvm-svn: 72709

ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.

llvm-svn: 72707

llvm-svn: 72706

llvm-svn: 72705

llvm-svn: 72698

llvm-svn: 72697

llvm-svn: 72696

llvm-svn: 72668

JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray

llvm-svn: 72631

llvm-svn: 72618

llvm-svn: 72604

llvm-svn: 72593

llvm-svn: 72558

decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.

Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.

llvm-svn: 72556

llvm-svn: 72535

llvm-svn: 72534

llvm-svn: 72531