llvm-svn: 24520

llvm-svn: 24517

enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516

llvm-svn: 24513

and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511

createPPCPatternInstructionSelector -> createPPCISelPattern

llvm-svn: 24510

llvm-svn: 24505

this to be something sane, but in the mean time it is unused, so safe to
make something bogus.

llvm-svn: 24504

llvm-svn: 24503

llvm-svn: 24501

llvm-svn: 24495

llvm-svn: 24492

next up: support argument passing in memory, not just registers

llvm-svn: 24490

Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489

llvm-svn: 24486

llvm-svn: 24485

llvm-svn: 24483

generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482

llvm-svn: 24481

llvm-svn: 24479

based on TargetType.

llvm-svn: 24478

llvm-svn: 24477

or native Win32

llvm-svn: 24476

conditionals.

llvm-svn: 24475

llvm-svn: 24473

llvm-svn: 24472

file.

llvm-svn: 24470

llvm-svn: 24469

llvm-svn: 24468

CPI ids

llvm-svn: 24467

CPI names

llvm-svn: 24466

llvm-svn: 24465

llvm-svn: 24462

due to basic blocks being misnamed.

llvm-svn: 24459

llvm-svn: 24458

llvm-svn: 24456

port to properly use L for the bb prefix instead of .

llvm-svn: 24454

llvm-svn: 24453

llvm-svn: 24452

llvm-svn: 24451