Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830

doing something clever.

llvm-svn: 23824

llvm-svn: 23740

from the .td file that correspond to it

llvm-svn: 23736

llvm-svn: 23533

llvm-svn: 23268

for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267

llvm-svn: 23266

llvm-svn: 23232

currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.

llvm-svn: 23230

llvm-svn: 23076

llvm-svn: 22707

llvm-svn: 21352

llvm-svn: 21351

them away.

llvm-svn: 21350

llvm-svn: 21349

llvm-svn: 21348

llvm-svn: 21347

llvm-svn: 21346

bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over

llvm-svn: 21345

  register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314

  register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295

llvm-svn: 21246

llvm-svn: 21226

Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225

All of Olden passes now! :)

llvm-svn: 18227

llvm-svn: 18225

correctly.

llvm-svn: 18200

36/42 SingleSource/UnitTests passing!

llvm-svn: 18199

them explicitly as well.

llvm-svn: 18193

llvm-svn: 18174

llvm-svn: 18170

llvm-svn: 18165

be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents

llvm-svn: 17183

the instruction binary format, all others are simply operands and should not
have the `field' label

llvm-svn: 16978

32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out

llvm-svn: 16163

llvm-svn: 16142

llvm-svn: 16121

llvm-svn: 16112

llvm-svn: 16107