Modified patch by Adam Preuss.

This builds on the existing framework for block tracing, edge profiling and optimal edge profiling.
See -help-hidden for new flags.
For documentation, see the technical report "Implementation of Path Profiling..." in llvm.org/pubs.

llvm-svn: 124515

llvm-svn: 124498

llvm-svn: 124497

zero effect on the testsuite (it improves two Ada testcases).

llvm-svn: 124496

Patch by Jyun-Yan You.

llvm-svn: 124492

benchmarks, and that it can be simplified to X/Y.  (In general you can only
simplify (Z*Y)/Y to Z if the multiplication did not overflow; if Z has the
form "X/Y" then this is the case).  This patch implements that transform and
moves some Div logic out of instcombine and into InstructionSimplify.
Unfortunately instcombine gets in the way somewhat, since it likes to change
(X/Y)*Y into X-(X rem Y), so I had to teach instcombine about this too.
Finally, thanks to the NSW/NUW flags, sometimes we know directly that "Z*Y"
does not overflow, because the flag says so, so I added that logic too.  This
eliminates a bunch of divisions and subtractions in 447.dealII, and has good
effects on some other benchmarks too.  It seems to have quite an effect on
tramp3d-v4 but it's hard to say if it's good or bad because inlining decisions
changed, resulting in massive changes all over.

llvm-svn: 124487

llvm-svn: 124486

llvm-svn: 124485

functionality change.

llvm-svn: 124482

llvm-svn: 124480

llvm-svn: 124479

llvm-svn: 124478

the function equality set.

llvm-svn: 124475

llvm-svn: 124472

llvm-svn: 124469

llvm-svn: 124468

llvm-svn: 124467

  branches. PR8575, rdar://5134905, rdar://8911460.
- Allow codegen tail duplication to dup small return blocks after register
  allocation is done.

llvm-svn: 124462

llvm-svn: 124458

only .syntax unified is supported.

llvm-svn: 124454

location was stated with FFI_INCLUDE_DIR/FFI_LIBRARY_DIR.

llvm-svn: 124449

[AVX] Clean up the code to configure target lowering for AVX.  Specify
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.

llvm-svn: 124447

llvm-svn: 124443

rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3

Added ResurrectKill to remove kill flags after we decide to reused a
physical register. And (hopefully) ensure that we call it in all the
right places.

Sorry, I'm not checking in a unit test given that it's a miscompile I
can't reproduce easily with a toy example. Failures in the rewriter
depend on a series of heuristic decisions maked during one of the many
upstream phases in codegen. This case would require coercing regalloc
to generate a couple of rematerialzations in a way that causes the
scavenger to reuse the same register at just the wrong point.

The general way to test this is to implement kill flags
verification. Then we could have a simple, robust compile-only unit
test. That would be worth doing if the whole pass was not about to
disappear. At this point we focus verification work on the next
generation of regalloc.

llvm-svn: 124442

llvm-svn: 124426

llvm-svn: 124406

llvm-svn: 124404

llvm-svn: 124397

Take 2. This includes fix for dragonegg crash.

llvm-svn: 124380

Add support for specifying register name in cfi-register/offset/def
as well as register number.

llvm-svn: 124379

Create override of this method in X86/ARM/MBlaze.

llvm-svn: 124378

llvm-svn: 124375

that relationships like "i8* null" is equivalent to "i32* null".

llvm-svn: 124368

Linear scan regalloc is currently assuming that any register aliased with
a member of a regclass must also be in at least one regclass.  That is not
always true.  For example, for X86, RIP is in a regclass but IP is not.
If you're unlucky, this can cause a crash by invalidating the iterator.

llvm-svn: 124365

if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357

CALL64 marks %xmm* as dead.

llvm-svn: 124354

llvm-svn: 124350

llvm-svn: 124346

llvm-svn: 124339

llvm-svn: 124331