llvm-svn: 96383

They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381

o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380

branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360

We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297

llvm-svn: 96288

IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255

change to SelectionDAG build APIs.

llvm-svn: 96230

as suggested by Bob Wilson.

llvm-svn: 96153

llvm-svn: 96075

created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069

llvm-svn: 96063

Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032

Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

llvm-svn: 96023

llvm-svn: 96019

llvm-svn: 96010

llvm-svn: 95999

MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955

llvm-svn: 95916

Sorry!

llvm-svn: 95892

A8.6.297

llvm-svn: 95885

llvm-svn: 95884

as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873

llvm-svn: 95784

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

A8.6.279

llvm-svn: 95713

A8.6.335 & A8.6.336

llvm-svn: 95703

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

For disassembly only.

A8.6.300

llvm-svn: 95669

llvm-svn: 95609

llvm-svn: 95603

The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584

llvm-svn: 95560

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548

Radar 7614112.

llvm-svn: 95456

llvm-svn: 95397

of const ones.  non-const ones aren't very useful, because you can't
even, say, emit them.

llvm-svn: 95205

llvm-svn: 95181

the end of the instruction instead of expecting the caller to
do it.  This currently causes the asm-verbose instruction 
comments to be on the next line.

llvm-svn: 95178