in tblgen.  This is PR2827, thanks to Waldemar Knorr for tracking this
down.

llvm-svn: 57124

llvm-svn: 56275

llvm-svn: 55878

Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.

llvm-svn: 55623

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

llvm-svn: 48412

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659

llvm-svn: 45419

llvm-svn: 40518

llvm-svn: 33539

llvm-svn: 32333

not be used for anything other than backwards compat constraint handling.

Add support for a new DisableEncoding property which contains a list of
registers that should not be encoded by the generated code emitter.  Convert
the codeemitter generator to use this, fixing some PPC JIT regressions.

llvm-svn: 31769

llvm-svn: 31403

llvm-svn: 30111

llvm-svn: 29137

2. Coalesce instruction cases.

llvm-svn: 29135

llvm-svn: 29122

from code emitter generation.

llvm-svn: 29097

llvm-svn: 26836

llvm-svn: 25669

for pointing this out!

llvm-svn: 23963

words.  There is no way for one of these targets to have a > 32-bit immediate!

llvm-svn: 22897

llvm-svn: 21428

* Reverse instruction bit components for a LittleEndian-style encoding
* Fix some comments and spacing

llvm-svn: 16975

Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137

llvm-svn: 15849

llvm-svn: 15627

llvm-svn: 15616

lib/Target/Sparc, we should not use it.

llvm-svn: 15603

llvm-svn: 15585

* Simplify code and shorten lines by not recomputing values

llvm-svn: 15582

* Shorten assert() text to make it fit within 80 cols

llvm-svn: 15508

llvm-svn: 15381

llvm-svn: 9903

llvm-svn: 9305

llvm-svn: 8875

llvm-svn: 8583

llvm-svn: 7640

llvm-svn: 7628