- Jul 01, 2009
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Daniel Dunbar authored
- This more or less amounts to a revert of r65379. I'm curious to know what happened that caused this variable to become unused. llvm-svn: 74579
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David Goodwin authored
llvm-svn: 74577
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David Goodwin authored
llvm-svn: 74566
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Bill Wendling authored
have the alignment be calculated up front, and have the back-ends obey whatever alignment is decided upon. This allows for future work that would allow for precise no-op placement and the like. llvm-svn: 74564
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David Goodwin authored
llvm-svn: 74555
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- Jun 30, 2009
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David Goodwin authored
llvm-svn: 74549
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David Greene authored
Add 256-bit memory operand support. llvm-svn: 74548
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David Goodwin authored
llvm-svn: 74543
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Rafael Espindola authored
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would cause one register to remain on the stack at the function return. llvm-svn: 74534
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Rafael Espindola authored
This was caused by me confounding FP0 and ST(0). llvm-svn: 74523
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Evan Cheng authored
Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
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Chris Lattner authored
llvm-svn: 74509
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Chris Lattner authored
llvm-svn: 74508
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Evan Cheng authored
llvm-svn: 74500
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David Greene authored
Add a 256-bit register class and YMM registers. llvm-svn: 74469
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David Goodwin authored
llvm-svn: 74468
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- Jun 29, 2009
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Rafael Espindola authored
Not sure I understand how the temp register gets used, but this fixes a bug and introduces no regressions. llvm-svn: 74446
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Owen Anderson authored
fence-atomic-fence down to just the atomic op. This is possible thanks to X86's relatively strong memory model, which guarantees that locked instructions (which are used to implement atomics) are implicit fences. llvm-svn: 74435
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David Greene authored
Add processor descriptions for Istanbul and Shanghai. llvm-svn: 74429
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David Greene authored
Fix a subtarget feature bug. llvm-svn: 74428
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David Greene authored
Add more vector ValueTypes for AVX and other extended vector instruction sets. llvm-svn: 74427
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David Goodwin authored
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. llvm-svn: 74423
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Duncan Sands authored
to make sure ThumbRegisterInfo.cpp are compiled and linked in. Patch by Xerxes. llvm-svn: 74421
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Evan Cheng authored
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. llvm-svn: 74420
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- Jun 27, 2009
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Anton Korobeynikov authored
llvm-svn: 74385
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Anton Korobeynikov authored
llvm-svn: 74384
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Douglas Gregor authored
llvm-svn: 74382
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Chris Lattner authored
target-specific operand printing functionality. Yay. llvm-svn: 74379
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Chris Lattner authored
llvm-svn: 74378
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Chris Lattner authored
llvm-svn: 74377
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Chris Lattner authored
llvm-svn: 74375
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Chris Lattner authored
a base register. We just ignore it for now. llvm-svn: 74374
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Chris Lattner authored
globals. This implements remat-constant.ll even without aggressive-remat. llvm-svn: 74373
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Chris Lattner authored
implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. llvm-svn: 74372
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Evan Cheng authored
llvm-svn: 74368
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Chris Lattner authored
llvm-svn: 74366
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David Goodwin authored
llvm-svn: 74357
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David Goodwin authored
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not. llvm-svn: 74355
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David Greene authored
Add feature flags for AVX and FMA and fix some SSE4A feature flag initialization problems. llvm-svn: 74350
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Evan Cheng authored
Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work. llvm-svn: 74336
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