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  1. Jul 01, 2009
  2. Jun 30, 2009
  3. Jun 29, 2009
    • Rafael Espindola's avatar
      FIX PR 4459. · 538064d6
      Rafael Espindola authored
      Not sure I understand how the temp register gets used,
      but this fixes a bug and introduces no regressions.
      
      llvm-svn: 74446
      538064d6
    • Owen Anderson's avatar
      Add a target-specific DAG combine on X86 to fold the common pattern of · 45c299ef
      Owen Anderson authored
      fence-atomic-fence down to just the atomic op.  This is possible thanks to
      X86's relatively strong memory model, which guarantees that locked instructions
      (which are used to implement atomics) are implicit fences.
      
      llvm-svn: 74435
      45c299ef
    • David Greene's avatar
      · 46b56ffa
      David Greene authored
      Add processor descriptions for Istanbul and Shanghai.
      
      llvm-svn: 74429
      46b56ffa
    • David Greene's avatar
      · a4b8998f
      David Greene authored
      Fix a subtarget feature bug.
      
      llvm-svn: 74428
      a4b8998f
    • David Greene's avatar
      · f92ba97c
      David Greene authored
      Add more vector ValueTypes for AVX and other extended vector instruction
      sets.
      
      llvm-svn: 74427
      f92ba97c
    • David Goodwin's avatar
      Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only... · dbf11ba8
      David Goodwin authored
      Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
      
      llvm-svn: 74423
      dbf11ba8
    • Duncan Sands's avatar
      Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt · 24a3724b
      Duncan Sands authored
      to make sure ThumbRegisterInfo.cpp are compiled and linked in.
      Patch by Xerxes.
      
      llvm-svn: 74421
      24a3724b
    • Evan Cheng's avatar
      Implement Thumb2 ldr. · b23b50d5
      Evan Cheng authored
      After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
      
      llvm-svn: 74420
      b23b50d5
  4. Jun 27, 2009
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