llvm-svn: 148239

llvm-svn: 148233

A fix for the previous commit: "integer constant is too large for ‘long’ type" error on some 32-bit bots

llvm-svn: 148232

Adding a basic ELF dynamic loader and MC-JIT for ELF. Functionality is currently basic and will be enhanced with future patches.
Patch developed by Andy Kaylor and Daniel Malea. Reviewed on llvm-commits.

llvm-svn: 148231

llvm-svn: 148230

Changed intrinsic ID operand to a target constant as its not used in any arithmetic so should not be checked in legalisation

llvm-svn: 148228

We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.

Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.

llvm-svn: 148225

llvm-svn: 148218

llvm-svn: 148217

llvm-svn: 148216

Fixup for r148132. Type replacement for LoopsProperties: from DenseMap to std::map, since we need to keep a valid pointer to properties of current loop.

Message for r148132:
LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache).

llvm-svn: 148215

or Clang is using this, and it would be hard to use it correctly given
the thread hostility of the function. Also, it never checked the return
which is rather dangerous with chdir. If someone was in fact using this,
please let me know, as well as what the usecase actually is so that
I can add it back and make it more correct and secure to use. (That
said, it's never going to be "safe" per-se, but we could at least
document the risks...)

llvm-svn: 148211

llvm-svn: 148206

llvm-svn: 148205

llvm-svn: 148196

Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.

llvm-svn: 148194

non-determinism in the 32 bit dragonegg buildbot.  Original commit
message:
Only emit the Leh_func_endN symbol when needed.

llvm-svn: 148191

Fixes PR11761: bad IR w/ redundant Phi elim

llvm-svn: 148177

llvm-svn: 148175

llvm-svn: 148174

llvm-svn: 148173

llvm-svn: 148172

llvm-svn: 148171

llvm-svn: 148170

live across BBs before register allocation. This miscompiled 197.parser
when a cmp + b are optimized to a cbnz instruction even though the CPSR def
is live-in a successor.
        cbnz    r6, LBB89_12
...
LBB89_12:
        ble     LBB89_1

The fix consists of two parts. 1) Teach LiveVariables that some unallocatable
registers might be liveouts so don't mark their last use as kill if they are.
2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional
branch does not kill CPSR.

rdar://10676853

llvm-svn: 148168

llvm-svn: 148167

llvm-svn: 148164

llvm-svn: 148156

The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.

This makes the call clobber lists longer, but I intend to get rid of
those soon.

llvm-svn: 148151

llvm-svn: 148150

llvm-svn: 148149

llvm-svn: 148143

Revert r148131, it was committed before it was ready.

llvm-svn: 148134

llvm-svn: 148133

LoopUnswitch: All helper data that is collected during loop-unswitch iterations was moved to separated class (LUAnalysisCache). 

llvm-svn: 148132

llvm-svn: 148131

Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.

llvm-svn: 148112

llvm-svn: 148109

Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.

llvm-svn: 148108

llvm-svn: 148106