(x + y) >> 1 gets changed to:
(x>>1) + (y>>1) + (x&y&1)

Saves us having to do any llvm assembly and overflow checking in the addition.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 188476

This happens in the caller a few frames up anyway.

llvm-svn: 188475

No functionality change, at best a slight (questionable) optimization,
but necessary for correctness of future work.

llvm-svn: 188474

- This line, and those below, will be ignored--

M    lib/ARCMigrate/ObjCMT.cpp

llvm-svn: 188473

Summary:
When the -dfsan-debug-nonzero-labels parameter is supplied, the code
is instrumented such that when a call parameter, return value or load
produces a nonzero label, the function __dfsan_nonzero_label is called.
The idea is that a debugger breakpoint can be set on this function
in a nominally label-free program to help identify any bugs in the
instrumentation pass causing labels to be introduced.

Reviewers: eugenis

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1405

llvm-svn: 188472

Reviewers: eugenis

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1406

llvm-svn: 188471

NS_ENUM, at least one power of 2 enumerator 
must be greater than two.

llvm-svn: 188470

llvm-svn: 188469

When a region is realloc()ed, MallocChecker records whether it was known
to be allocated or not. If it is, and the reallocation fails, the original
region has to be freed. Previously, when an allocated region escaped,
MallocChecker completely stopped tracking it, so a failed reallocation
still (correctly) wouldn't require freeing the original region. Recently,
however, MallocChecker started tracking escaped symbols, so that if it were
freed we could check that the deallocator matched the allocator. This
broke the reallocation model for whether or not a symbol was allocated.

Now, MallocChecker will actually check if a symbol is owned, and only
require freeing after a failed reallocation if it was owned before.

PR16730

llvm-svn: 188468

llvm-svn: 188467

1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing

llvm-svn: 188466

llvm-svn: 188465

Add support for half (a.k.a. __fp16) in builtin descriptions. 
The second argument to BUILTIN() now accepts 'h' to represent half.

Patch by Daniel Sanders

llvm-svn: 188464

llvm-svn: 188463

llvm-svn: 188462

Includes:
add.a, adds_a, adds_s, adds_u, addv, addvi, andi.b, asub_[su], ave_[su],
aver_[su], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bset,
bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw],
div_[su], dotp_[su], dpadd_[su], dpsub_[su], fadd, fceq, fclass, fcl[et], fcne,
fdiv, fexp2, ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, fseq, fsle, fslt, fsne, fsqr, fsub, ftint_[su],
ftq, ilvev, ilvl, ilvod, ilvr, ldi, frcp, frsqrt, madd_q, maddr_q, maddv,
max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv,
mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf,
sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subv, subvi,
xori


Patch by Daniel Sanders

llvm-svn: 188461

Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori

Patch by Daniel Sanders

llvm-svn: 188460

llvm-svn: 188459

Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders

llvm-svn: 188458

Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders

llvm-svn: 188457

llvm-svn: 188456

llvm-svn: 188455

Revert r188449 as it turns out we're just missing the instructions that need the v16i32/v16f32 matching.

llvm-svn: 188454

llvm-svn: 188453

llvm-svn: 188452

llvm-svn: 188451

Summary:
There were several things going wrong:
- We mangled in useless qualifiers like "volatile void" return types.
- We didn't propagate 64-bit pointer markers sufficiently.
- We mangled qualifiers belonging to the pointee incorrectly.

This fixes PR16844 and PR16848.

Reviewers: rnk, whunt

Reviewed By: rnk

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1353

llvm-svn: 188450

Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask.

llvm-svn: 188449

llvm-svn: 188448

llvm-svn: 188447

llvm-svn: 188446

llvm-svn: 188445

We were marking both LLVMBUILDOUTPUT and LLVMBUILDERRORS as
ERROR_VARIABLES when clearly LLVMBUILDOUTPUT should be marked as
OUTPUT_VARIABLE.

llvm-svn: 188444

where the executable has been slid.  This detects the regression fixed in
r188289.

llvm-svn: 188443

llvm-svn: 188442

Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().

llvm-svn: 188441

Also use the more common "derive from" in place of "extend" in another
comment.

llvm-svn: 188440

llvm-svn: 188439

properties (direct or indirect) setter/getter (or declared 
methods as well) are seen by the method implementation type 
matching logic before declaration of method in super class 
is seen. This fixes the warning coming out of that method mismatch.
// rdar://14650159

llvm-svn: 188438

When new virtual registers are created during splitting/spilling, defer
creation of the live interval until we need to use the live interval.

Along with the recent commits to notify LiveRangeEdit when new virtual
registers are created, this makes it possible for functions like
TargetInstrInfo::loadRegFromStackSlot() and
TargetInstrInfo::storeRegToStackSlot() to create multiple virtual
registers as part of the process of generating loads/stores for
different register classes, and then have the live intervals for those
new registers computed when they are needed.

llvm-svn: 188437