that brings us to 80-col violations
or tabs.

Usage:
  visit-violations <file>

At the moment it outputs editor invocations.

llvm-svn: 55509

llvm-svn: 55508

whose darwin code was written after the ability to dynamically register frames,
we need to do special hacks to make things work.

llvm-svn: 55507

llvm-svn: 55506

llvm-svn: 55504

llvm-svn: 55500

In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN

llvm-svn: 55499

its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498

SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

llvm-svn: 55497

were being emitted after the first instructions of the entry block.

llvm-svn: 55496

llvm-svn: 55486

llvm-svn: 55483

Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.

llvm-svn: 55482

Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

llvm-svn: 55480

llvm-svn: 55478

FastEmitInst_extractsubreg doesn't need to be passed the register class.  It can get it from MachineRegisterInfo instead.

llvm-svn: 55476

Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475

llvm-svn: 55471

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

llvm-svn: 55467

llvm-svn: 55466

for operands: rdar://6179606.  no testcase, because I can't write
a .ll file that is this broken ;-)

llvm-svn: 55460

Prakash Prabhu!

llvm-svn: 55458

ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457

Feel free to fix a better way!

llvm-svn: 55456

llvm-svn: 55451

works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.

llvm-svn: 55450

llvm-svn: 55439

SSE2 registers as well as the MMX registers.

llvm-svn: 55436

llvm" for consistency.

llvm-svn: 55435

llvm-svn: 55434

llvm-svn: 55433

llvm-svn: 55432

llvm-svn: 55431

llvm-svn: 55430

llvm-svn: 55429

Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.

llvm-svn: 55428

just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.

llvm-svn: 55427

the details of materializing constants and other values into
registers, and make use of it in several places.

llvm-svn: 55426

llvm-svn: 55425

llvm-svn: 55424