model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847

the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.

llvm-svn: 37844

llvm-svn: 37801

llvm-svn: 37786

llvm-svn: 37784

llvm-svn: 37756

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719

between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718

llvm-svn: 37717

llvm-svn: 37716

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704

llvm-svn: 37700

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

Anton for half of this patch.

llvm-svn: 37641

Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.

llvm-svn: 37636

llvm-svn: 37625

define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617

llvm-svn: 37611

llvm-svn: 37579

llvm-svn: 37578

implementation for x86.

llvm-svn: 37576

llvm-svn: 37574

llvm-svn: 37571

llvm-svn: 37534

llvm-svn: 37533

llvm-svn: 37528

llvm-svn: 37419

llvm-svn: 37320

llvm-svn: 37275

llvm-svn: 37266

llvm-svn: 37239

llvm-svn: 37234

llvm-svn: 37193

Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.

llvm-svn: 37173

llvm-svn: 37172

cause other regressions.

llvm-svn: 37160

llvm-svn: 37159

llvm-svn: 37154

llvm-svn: 37141