Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309

This pass forward branches through conditions when it can show that the
conditions is either always true or false for a predecessor.  This currently
only handles the most simple cases of this, but is successful at threading
across 2489 branches and 65 switch instructions in 176.gcc, which isn't bad.

llvm-svn: 21306

llvm-svn: 21303

a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases

llvm-svn: 21302

easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything

llvm-svn: 21300

llvm-svn: 21299

This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298

in the PPC Pattern ISel

llvm-svn: 21297

llvm-svn: 21296

  register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295

now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294

  where it is safe to do so.

llvm-svn: 21293

Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291

llvm-svn: 21289

llvm-svn: 21288

with != 0 comparisons vanishing.

llvm-svn: 21287

llvm-svn: 21286

llvm-svn: 21285

* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282

llvm-svn: 21281

Note that this probably only works for little endian targets, but is enough
to get siod working :)

llvm-svn: 21280

  0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279

llvm-svn: 21276

llvm-svn: 21275

Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274

llvm-svn: 21273

llvm-svn: 21272

llvm-svn: 21271

like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270

things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269

andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268

llvm-svn: 21267

SelectionDAG to do the job with AND.  Don't legalize Z_E_I anymore as
it is gone

llvm-svn: 21266

instead.  OVerall, this increases the amount of folding we can do.

llvm-svn: 21265

llvm-svn: 21262

Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261

Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260

llvm-svn: 21258

llvm-svn: 21255

llvm-svn: 21253