llvm-svn: 148869

llvm-svn: 148864

llvm-svn: 148862

llvm-svn: 148836

Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.

llvm-svn: 148833

llvm-svn: 148832

llvm-svn: 148821

llvm-svn: 148819

llvm-svn: 148818

llvm-svn: 148815

llvm-svn: 148805

  v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.

llvm-svn: 148803

This pacifies machine verifier

llvm-svn: 148782

Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.

llvm-svn: 148771

llvm-svn: 148764

llvm-svn: 148762

llvm-svn: 148761

violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759

llvm-svn: 148757

llvm-svn: 148755

llvm-svn: 148751

llvm-svn: 148748

llvm-svn: 148745

llvm-svn: 148742

llvm-svn: 148737

llvm-svn: 148734

llvm-svn: 148721

Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718

llvm-svn: 148712

llvm-svn: 148694

llvm-svn: 148687

This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686

llvm-svn: 148685

Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.

llvm-svn: 148684

Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.

llvm-svn: 148672

llvm-svn: 148670

Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.

llvm-svn: 148667

Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class.

llvm-svn: 148665

Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.

llvm-svn: 148664

Patch by Ana Pazos!

llvm-svn: 148658