llvm-svn: 59344

llvm-svn: 59234

llvm-svn: 59107

llvm-svn: 59104

llvm-svn: 59102

llvm-svn: 59088

llvm-svn: 59084

llvm-svn: 59074

llvm-svn: 59016

llvm-svn: 58800

llvm-svn: 56126

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017

llvm-svn: 45821

llvm-svn: 45727

llvm-svn: 45667

llvm-svn: 45656

llvm-svn: 45653

llvm-svn: 45418

Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.

llvm-svn: 44960

llvm-svn: 41863

llvm-svn: 40887

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 38501

llvm-svn: 37965

Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.

llvm-svn: 37895

llvm-svn: 37468

For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.

llvm-svn: 37351

llvm-svn: 37066

llvm-svn: 36948

llvm-svn: 36909

llvm-svn: 36693

llvm-svn: 36660

llvm-svn: 33353