spilled value is available for reuse.

llvm-svn: 41067

llvm-svn: 41064

Re-implement trivial rematerialization. This allows def MIs whose live intervals that are coalesced to be rematerialized.

llvm-svn: 41060

llvm-svn: 41043

llvm-svn: 41024

llvm-svn: 41016

Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.

llvm-svn: 41005

use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.

llvm-svn: 40987

llvm-svn: 40986

llvm-svn: 40976

llvm-svn: 40975

llvm-svn: 40965

(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958

to do so.

llvm-svn: 40955

llvm-svn: 40925

llvm-svn: 40921

- Fix some minor bugs related to special markers on val# def. ~0U means
  undefined, ~1U means dead val#.

llvm-svn: 40916

llvm-svn: 40914

kill instruction #, and source register number (iff the value# is defined by a
copy).
- Now def instruction # is set for every value#, not just for copy defined ones.
- Update some outdated code related inactive live ranges.
- Kill info not yet set. That's next patch.

llvm-svn: 40913

Add a missing forward declaration.

llvm-svn: 40896

introduced by chandler's patch.

llvm-svn: 40864

llvm-svn: 40863

llvm-svn: 40854

llvm-svn: 40843

This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.

This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807

llvm-svn: 40757

llvm-svn: 40748

llvm-svn: 40722

llvm-svn: 40712

simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)

Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)

And let scheduledag emit the move from X86::EAX to a virtual register.

llvm-svn: 40710

llvm-svn: 40688

llvm-svn: 40682

New CallInst interface to address GLIBCXX_DEBUG errors caused by
indexing an empty std::vector.

Updates to all clients.

llvm-svn: 40660

llvm-svn: 40654

- Fixed an existing unexpanded tab.

llvm-svn: 40605

llvm-svn: 40598

for prettiness.

llvm-svn: 40593

still under discussion.

llvm-svn: 40549

llvm-svn: 40548

offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.

llvm-svn: 40534