llvm-svn: 137195

llvm-svn: 137194

llvm-svn: 137193

llvm-svn: 137192

llvm-svn: 137191

These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.

llvm-svn: 137190

llvm-svn: 137189

llvm-svn: 137188

llvm-svn: 137187

CFString.py now shows contents in a more NSString-like way (e.g. you get @"Hello" instead of "Hello")
new --raw-output (-R) option to frame variable prevents using summaries and synthetic children
 other future formatting enhancements will be excluded by using the -R option
 test case enhanced to check that -R works correctly

llvm-svn: 137185

llvm-svn: 137184

On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

llvm-svn: 137182

llvm-svn: 137180

llvm-svn: 137179

llvm-svn: 137178

llvm-svn: 137177

llvm-svn: 137176

VMCore/BasicBlock.cpp: Don't assume BasicBlock::iterator might end with a non-PHInode Instruction in successors.

Frontends(eg. clang) might pass incomplete form of IR, to step off the way beyond iterator end. In the case I had met, it took infinite loop due to meeting bogus PHInode.

Thanks to Jay Foad and John McCall.

llvm-svn: 137175

llvm-svn: 137174

llvm-svn: 137173

llvm-svn: 137172

Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.

llvm-svn: 137171

llvm-svn: 137170

llvm-svn: 137169

Create a new register class for the set of all GPRs except the PC.  Use it to tighten our decoding of BFI.

llvm-svn: 137168

types instead of letting Clang crash.

llvm-svn: 137167

llvm-svn: 137166

llvm-svn: 137165

llvm-svn: 137164

llvm-svn: 137163

llvm-svn: 137162

is the best we can do for these patterns. This fix PR10554.

llvm-svn: 137161

llvm-svn: 137160

functionality since in the C api a pass is created and added to a pass
manager in a single call.

llvm-svn: 137159

Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms.
That's obviously bogus.
For example,

 .globl _foo
 .equ _foo, 0x987654321ULL


rdar://9922863

llvm-svn: 137158

used a log unchecked.

llvm-svn: 137157

Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156

llvm-svn: 137154

llvm-svn: 137153

The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.

llvm-svn: 137151