llvm-svn: 113610

understand (the log file was no help).

llvm-svn: 113605

that the memoperands are properly set after DAG building and general mucking
about.

llvm-svn: 113585

llvm-svn: 113224

Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment

llvm-svn: 112694

llvm-svn: 112661

llvm-svn: 112642

general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.

llvm-svn: 111691

llvm-svn: 111041

Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744

llvm-svn: 110468

Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)

llvm-svn: 109063

llvm-svn: 108769

Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
utility classes can be used from multiple files.  This will aid
transitioning to a new refactored x86 SIMD specification.

llvm-svn: 108213

TableGen fragment refactoring.

Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727