Commits · 7a6e8f2c5d3397113d305c57fd04b28fc0c7cc96 · Roger Ferrer / llvm-epi-0.8

Sep 27, 2011
- Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). · af136f71
  Jim Grosbach authored Sep 27, 2011
```
Naming conventions consistency. No functional change.

llvm-svn: 140636
```
  af136f71
- PTX: Fix case where printed alignment could be 0 · 4f7054e5
  Justin Holewinski authored Sep 27, 2011
```
llvm-svn: 140624
```
  4f7054e5
- PTX: Use external symbols to keep track of params and locals. This also fixes · e0745934
  Justin Holewinski authored Sep 27, 2011
```
a couple of outstanding issues with frame objects occuring as instruction
operands.

llvm-svn: 140616
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  e0745934
- Use existing function. · 1c759769
  Jakob Stoklund Olesen authored Sep 27, 2011
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llvm-svn: 140615
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  1c759769
- Fix function MipsRegisterInfo::getRegisterNumbering. · e41b1d59
  Akira Hatanaka authored Sep 27, 2011
```
Return numbers of 64-bit registers.

llvm-svn: 140609
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  e41b1d59
- Do not add the pass that restores $gp if target is Mips64. · ff5d0965
  Akira Hatanaka authored Sep 27, 2011
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llvm-svn: 140607
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  ff5d0965
- Mark MipsPseudo isPseudo. · bb050745
  Akira Hatanaka authored Sep 27, 2011
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llvm-svn: 140598
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  bb050745
- PTX: Add support for sitofp in backend · 9f01f893
  Justin Holewinski authored Sep 27, 2011
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llvm-svn: 140593
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  9f01f893
- Remove extraneous commit garbage. · b1a9f654
  Owen Anderson authored Sep 26, 2011
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llvm-svn: 140581
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  b1a9f654
Sep 26, 2011
- Set register class of a register according to value of HasMips64. · a6a9c20c
  Akira Hatanaka authored Sep 26, 2011
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llvm-svn: 140570
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  a6a9c20c
- Define variable HasMips64 in MipsTargetLowering. · 7b502920
  Akira Hatanaka authored Sep 26, 2011
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llvm-svn: 140569
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  7b502920
- In single float mode, double precision FP arguments are passed in integer · e5ce7090
  Akira Hatanaka authored Sep 26, 2011
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registers, so there is no need to check here.

llvm-svn: 140568
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  e5ce7090
- ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. · f01e2de5
  Owen Anderson authored Sep 26, 2011
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llvm-svn: 140560
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  f01e2de5
- PTX: Fix memcpy intrinsic to handle 64-bit pointers · da2919db
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140556
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  da2919db
- PTX: Implement PTXSelectionDAGInfo · b40da7f9
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140549
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  b40da7f9
- PTX: Implement ISD::ANY_EXTEND · c3edaddf
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140548
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  c3edaddf
- PTX: Fix detection of stack load/store vs. global load/store, as well as fix the · 1395cf84
  Justin Holewinski authored Sep 26, 2011
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printing of local offsets

llvm-svn: 140547
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  1395cf84
- PTX: SM > 2.0 implies +double · f8dd701b
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140536
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  f8dd701b
- PTX: Fix some lingering issues with stack allocation · 14defde0
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140535
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  14defde0
- PTX: Split up the TableGen instruction definitions into logical units · 37fd8767
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140534
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  37fd8767
- PTX: Unify handling of loads/stores · d40f5aba
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140533
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  d40f5aba
- PTX: Handle FrameIndex nodes · 8c800193
  Justin Holewinski authored Sep 26, 2011
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llvm-svn: 140532
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  8c800193
- PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL... · b1fbf9ff
  David Meyer authored Sep 26, 2011
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PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval

llvm-svn: 140516
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  b1fbf9ff
- Fix VEX decoding in i386 mode. Fixes PR11008. · 45faba98
  Craig Topper authored Sep 26, 2011
```
llvm-svn: 140515
```
  45faba98
Sep 25, 2011
- Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos. · fd719d18
  Jakob Stoklund Olesen authored Sep 25, 2011
```
No functional change intended.

llvm-svn: 140470
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  fd719d18
Sep 24, 2011
- Add .td file. · 7d7ee0c3
  Akira Hatanaka authored Sep 24, 2011
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llvm-svn: 140446
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  7d7ee0c3
- Preparation for adding simple Mips64 instructions. · e96273e7
  Akira Hatanaka authored Sep 24, 2011
```
llvm-svn: 140443
```
  e96273e7
- Only run MF.verify() with EXPENSIVE_CHECKS=1. · 55cf2ed1
  Jakob Stoklund Olesen authored Sep 24, 2011
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llvm-svn: 140441
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  55cf2ed1
- Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. · 4916840e
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140426
```
  4916840e
- Also match negative offsets for addrmode3 and addrmode5. · 2056d15b
  Jakob Stoklund Olesen authored Sep 23, 2011
```
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

llvm-svn: 140425
```
  2056d15b
Sep 23, 2011
- Add more fixed bits to USAT16 encoding to filter out incorrect decodings. · b0b865d6
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140422
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  b0b865d6
- Post-index loads/stores in still need to print the post-indexed immediate,... · 737beaf8
  Owen Anderson authored Sep 23, 2011
```
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.

llvm-svn: 140420
```
  737beaf8
- Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. · 987a8789
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140415
```
  987a8789
- Revert r140412. This affects more instructions than intended. · ffa8428a
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140413
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  ffa8428a
- Thumb2 register-shifted-register loads cannot target the PC or the SP. · 7591d0c3
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140412
```
  7591d0c3
- Implement N32/64 calling convention. Patch by Liu. · d6af2c62
  Akira Hatanaka authored Sep 23, 2011
```
llvm-svn: 140401
```
  d6af2c62
- Make FGR64RegisterClass available if target is Mips64. · ceb55e72
  Akira Hatanaka authored Sep 23, 2011
```
llvm-svn: 140397
```
  ceb55e72
- Add definitions of 64-bit register files. Add code for returning Mips64's sets of · 77709a67
  Akira Hatanaka authored Sep 23, 2011
```
callee-saved registers and reserved registers.

llvm-svn: 140395
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  77709a67
- PTX: Fix parameter order bug · 71d32c98
  Justin Holewinski authored Sep 23, 2011
```
llvm-svn: 140394
```
  71d32c98
- Fix a couple of 80 column violations. · 24e45cab
  Wesley Peck authored Sep 23, 2011
```
patch contributed by Jia Liu!

llvm-svn: 140391
```
  24e45cab